DE69027271T2 - Halbleiteranordnung mit E2PROM und EPROM in einem Chip - Google Patents

Halbleiteranordnung mit E2PROM und EPROM in einem Chip

Info

Publication number
DE69027271T2
DE69027271T2 DE69027271T DE69027271T DE69027271T2 DE 69027271 T2 DE69027271 T2 DE 69027271T2 DE 69027271 T DE69027271 T DE 69027271T DE 69027271 T DE69027271 T DE 69027271T DE 69027271 T2 DE69027271 T2 DE 69027271T2
Authority
DE
Germany
Prior art keywords
e2prom
eprom
chip
semiconductor arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69027271T
Other languages
English (en)
Other versions
DE69027271D1 (de
Inventor
Teruo Uemura
Takahide Mizutani
Naoki Hanada
Tatsuo Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69027271D1 publication Critical patent/DE69027271D1/de
Publication of DE69027271T2 publication Critical patent/DE69027271T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69027271T 1989-10-11 1990-10-10 Halbleiteranordnung mit E2PROM und EPROM in einem Chip Expired - Fee Related DE69027271T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1264453A JPH088314B2 (ja) 1989-10-11 1989-10-11 不揮発性半導体記憶装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE69027271D1 DE69027271D1 (de) 1996-07-11
DE69027271T2 true DE69027271T2 (de) 1996-12-19

Family

ID=17403414

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69027271T Expired - Fee Related DE69027271T2 (de) 1989-10-11 1990-10-10 Halbleiteranordnung mit E2PROM und EPROM in einem Chip

Country Status (5)

Country Link
US (1) US5200636A (de)
EP (1) EP0422606B1 (de)
JP (1) JPH088314B2 (de)
KR (1) KR940006588B1 (de)
DE (1) DE69027271T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355007A (en) * 1990-11-23 1994-10-11 Texas Instruments Incorporated Devices for non-volatile memory, systems and methods
KR940009644B1 (ko) * 1991-11-19 1994-10-15 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법
JP3273582B2 (ja) 1994-05-13 2002-04-08 キヤノン株式会社 記憶装置
US5498560A (en) * 1994-09-16 1996-03-12 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
JP3762433B2 (ja) * 1994-10-28 2006-04-05 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体装置及び不揮発性メモリ
US6787844B2 (en) * 1995-09-29 2004-09-07 Nippon Steel Corporation Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
EP0802569B1 (de) * 1996-04-15 2003-09-24 STMicroelectronics S.r.l. Mit einem EEPROM integrierter FLASH-EPROM
EP0994512B1 (de) 1998-10-15 2004-09-22 STMicroelectronics S.r.l. Verfahren zum Herstellen von nicht selbstausgerichteten, FLOTOX-EEPROM-speicherzellen
JP3314807B2 (ja) 1998-11-26 2002-08-19 日本電気株式会社 半導体装置の製造方法
US6903434B2 (en) 1999-05-20 2005-06-07 Alliance Semiconductors Method and apparatus for integrating flash EPROM and SRAM cells on a common substrate
TW529160B (en) * 2000-12-22 2003-04-21 Koninkl Philips Electronics Nv Semiconductor device comprising an electrically erasable programmable read only memory and a flash-erasable programmable read only memory, and method of manufacturing such a semiconductor device
KR100375232B1 (ko) * 2001-03-20 2003-03-08 삼성전자주식회사 비휘발성 메모리 소자의 제조방법
JP2003282823A (ja) * 2002-03-26 2003-10-03 Toshiba Corp 半導体集積回路
WO2004023385A1 (ja) * 2002-08-29 2004-03-18 Renesas Technology Corp. 半導体処理装置及びｉｃカード
JP2004200553A (ja) 2002-12-20 2004-07-15 Fujitsu Ltd 半導体装置及びその製造方法
KR100604850B1 (ko) * 2003-05-20 2006-07-31 삼성전자주식회사 균일하지 않은 채널 유전막 두께를 갖는 이이피롬 셀 구조및 그 제조방법
US7256449B2 (en) * 2003-05-20 2007-08-14 Samsung Electronics, Co., Ltd. EEPROM device for increasing a coupling ratio and fabrication method thereof
US20040232476A1 (en) * 2003-05-20 2004-11-25 Kang Sung-Taeg EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same
US6998304B2 (en) * 2004-03-01 2006-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for integrated manufacturing of split gate flash memory with high voltage MOSFETS

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4393474A (en) * 1979-10-26 1983-07-12 Texas Instruments Incorporated EPROM and RAM cell layout with equal pitch for use in fault tolerant memory device or the like
JPS58166596A (ja) * 1982-03-26 1983-10-01 Mitsubishi Electric Corp 半導体不揮発性記憶装置
JPS596581A (ja) * 1982-07-02 1984-01-13 Mitsubishi Electric Corp 半導体不揮発性記憶装置
US4613956A (en) * 1983-02-23 1986-09-23 Texas Instruments Incorporated Floating gate memory with improved dielectric
JPS60189971A (ja) * 1984-03-09 1985-09-27 Toshiba Corp 半導体装置の製造方法
US4698787A (en) * 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
FR2623651B1 (fr) * 1987-11-20 1992-11-27 Sgs Thomson Microelectronics Plan memoire et procede et prototype de definition d'un circuit integre electronique comportant un tel plan memoire
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
DE3816358A1 (de) * 1988-05-13 1989-11-23 Eurosil Electronic Gmbh Nichtfluechtige speicherzelle und verfahren zur herstellung
JP2790461B2 (ja) * 1988-05-20 1998-08-27 株式会社日立製作所 半導体集積回路装置
JPH02297970A (ja) * 1989-05-12 1990-12-10 Hitachi Ltd 半導体集積回路装置

Also Published As

Publication number Publication date
DE69027271D1 (de) 1996-07-11
EP0422606A3 (en) 1992-01-22
KR910008847A (ko) 1991-05-31
US5200636A (en) 1993-04-06
KR940006588B1 (ko) 1994-07-22
EP0422606A2 (de) 1991-04-17
JPH088314B2 (ja) 1996-01-29
JPH03126265A (ja) 1991-05-29
EP0422606B1 (de) 1996-06-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee