DE3885185D1 - Vertikal-Trench-Transistor-/Kapazitätsspeicherzellen-Struktur und Herstellungsverfahren dafür. - Google Patents

Vertikal-Trench-Transistor-/Kapazitätsspeicherzellen-Struktur und Herstellungsverfahren dafür.

Info

Publication number
DE3885185D1
DE3885185D1 DE88109622T DE3885185T DE3885185D1 DE 3885185 D1 DE3885185 D1 DE 3885185D1 DE 88109622 T DE88109622 T DE 88109622T DE 3885185 T DE3885185 T DE 3885185T DE 3885185 D1 DE3885185 D1 DE 3885185D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory cell
cell structure
method therefor
vertical trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE88109622T
Other languages
German (de)
English (en)
Inventor
Wei Hwang
Chau-Chun Nicky Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3885185D1 publication Critical patent/DE3885185D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE88109622T 1987-08-03 1988-06-16 Vertikal-Trench-Transistor-/Kapazitätsspeicherzellen-Struktur und Herstellungsverfahren dafür. Expired - Lifetime DE3885185D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/081,270 US4833516A (en) 1987-08-03 1987-08-03 High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor

Publications (1)

Publication Number Publication Date
DE3885185D1 true DE3885185D1 (de) 1993-12-02

Family

ID=22163129

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88109622T Expired - Lifetime DE3885185D1 (de) 1987-08-03 1988-06-16 Vertikal-Trench-Transistor-/Kapazitätsspeicherzellen-Struktur und Herstellungsverfahren dafür.

Country Status (7)

Country Link
US (1) US4833516A (enExample)
EP (1) EP0302204B1 (enExample)
JP (1) JPS6445160A (enExample)
AU (1) AU609167B2 (enExample)
BR (1) BR8803628A (enExample)
CA (1) CA1289266C (enExample)
DE (1) DE3885185D1 (enExample)

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JP2606857B2 (ja) * 1987-12-10 1997-05-07 株式会社日立製作所 半導体記憶装置の製造方法
JPH01227468A (ja) * 1988-03-08 1989-09-11 Oki Electric Ind Co Ltd 半導体記憶装置
US4954854A (en) * 1989-05-22 1990-09-04 International Business Machines Corporation Cross-point lightly-doped drain-source trench transistor and fabrication process therefor
JP2623850B2 (ja) * 1989-08-25 1997-06-25 富士電機株式会社 伝導度変調型ｍｏｓｆｅｔ
US5034787A (en) * 1990-06-28 1991-07-23 International Business Machines Corporation Structure and fabrication method for a double trench memory cell device
JP2932635B2 (ja) * 1990-08-11 1999-08-09 日本電気株式会社 半導体記憶装置
US5198995A (en) * 1990-10-30 1993-03-30 International Business Machines Corporation Trench-capacitor-one-transistor storage cell and array for dynamic random access memories
TW313677B (enExample) * 1991-08-14 1997-08-21 Gold Star Electronics
JP3896158B2 (ja) * 1993-02-04 2007-03-22 コーネル・リサーチ・ファウンデーション・インコーポレイテッド マイクロ構造及びその製造のためのシングルマスク、単結晶プロセス
KR0123751B1 (ko) * 1993-10-07 1997-11-25 김광호 반도체장치 및 그 제조방법
US5605862A (en) * 1995-04-05 1997-02-25 International Business Machines Corporation Process for making low-leakage contacts
EP0905783B1 (en) * 1997-09-30 2006-06-14 Infineon Technologies AG Vertical transistor implemented in a memory cell comprising a trench capacitor
US5990511A (en) * 1997-10-16 1999-11-23 International Business Machines Corporation Memory cell with transfer device node in selective polysilicon
US6236079B1 (en) 1997-12-02 2001-05-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device having a trench capacitor
US6069390A (en) 1998-01-15 2000-05-30 International Business Machines Corporation Semiconductor integrated circuits with mesas
US6177299B1 (en) 1998-01-15 2001-01-23 International Business Machines Corporation Transistor having substantially isolated body and method of making the same
US5831301A (en) * 1998-01-28 1998-11-03 International Business Machines Corp. Trench storage dram cell including a step transfer device
US6172390B1 (en) 1998-03-25 2001-01-09 Siemens Aktiengesellschaft Semiconductor device with vertical transistor and buried word line
DK1079851T3 (da) * 1998-05-12 2007-09-24 Greenville Hospital System Anvendelse af anti-prolactinmidler til behandling af cancer
US6037620A (en) * 1998-06-08 2000-03-14 International Business Machines Corporation DRAM cell with transfer device extending along perimeter of trench storage capacitor
US6121651A (en) * 1998-07-30 2000-09-19 International Business Machines Corporation Dram cell with three-sided-gate transfer device
JP3024641B1 (ja) 1998-10-23 2000-03-21 日本電気株式会社 シャドウマスク及びその製造方法並びにシャドウマスクを用いた有機ｅｌディスプレイの製造方法
US6144054A (en) 1998-12-04 2000-11-07 International Business Machines Corporation DRAM cell having an annular signal transfer region
US6440794B1 (en) 1999-05-28 2002-08-27 International Business Machines Corporation Method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique
US6690038B1 (en) 1999-06-05 2004-02-10 T-Ram, Inc. Thyristor-based device over substrate surface
US6245615B1 (en) * 1999-08-31 2001-06-12 Micron Technology, Inc. Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
US6383871B1 (en) * 1999-08-31 2002-05-07 Micron Technology, Inc. Method of forming multiple oxide thicknesses for merged memory and logic applications
US6740555B1 (en) 1999-09-29 2004-05-25 Infineon Technologies Ag Semiconductor structures and manufacturing methods
US6271080B1 (en) 1999-12-16 2001-08-07 International Business Machines Corporation Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity
US6288422B1 (en) 2000-03-31 2001-09-11 International Business Machines Corporation Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance
US6281539B1 (en) 2000-03-31 2001-08-28 International Business Machines Corporation Structure and process for 6F2 DT cell having vertical MOSFET and large storage capacitance
US6358867B1 (en) 2000-06-16 2002-03-19 Infineon Technologies Ag Orientation independent oxidation of silicon
JP3808700B2 (ja) * 2000-12-06 2006-08-16 株式会社東芝 半導体装置及びその製造方法
US6916745B2 (en) * 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6727528B1 (en) 2001-03-22 2004-04-27 T-Ram, Inc. Thyristor-based device including trench dielectric isolation for thyristor-body regions
US7456439B1 (en) 2001-03-22 2008-11-25 T-Ram Semiconductor, Inc. Vertical thyristor-based memory with trench isolation and its method of fabrication
US6620676B2 (en) * 2001-06-29 2003-09-16 International Business Machines Corporation Structure and methods for process integration in vertical DRAM cell fabrication
US6965129B1 (en) 2002-11-06 2005-11-15 T-Ram, Inc. Thyristor-based device having dual control ports
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7485910B2 (en) * 2005-04-08 2009-02-03 International Business Machines Corporation Simplified vertical array device DRAM/eDRAM integration: method and structure
US20090159947A1 (en) * 2007-12-19 2009-06-25 International Business Machines Corporation SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US9812443B1 (en) 2017-01-13 2017-11-07 International Business Machines Corporation Forming vertical transistors and metal-insulator-metal capacitors on the same chip

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Publication number Priority date Publication date Assignee Title
US3883948A (en) * 1974-01-02 1975-05-20 Signetics Corp Semiconductor structure and method
DE3174468D1 (en) * 1980-09-17 1986-05-28 Hitachi Ltd Semiconductor device and method of manufacturing the same
JPS583269A (ja) * 1981-06-30 1983-01-10 Fujitsu Ltd 縦型ｍｏｓダイナミツクメモリ−セル
JPS5919366A (ja) * 1982-07-23 1984-01-31 Hitachi Ltd 半導体記憶装置
JPS5982761A (ja) * 1982-11-04 1984-05-12 Hitachi Ltd 半導体メモリ
JPS60223153A (ja) * 1984-04-19 1985-11-07 Nippon Telegr & Teleph Corp <Ntt> Ｍｉｓ型キャパシタを有する半導体装置の製法
EP0167764B1 (en) * 1984-06-14 1989-08-16 International Business Machines Corporation Dynamic ram cell
JPS61179571A (ja) * 1984-09-27 1986-08-12 テキサス　インスツルメンツ　インコ−ポレイテツド メモリセルおよびそのアレイ
DE3585136D1 (de) * 1984-10-31 1992-02-20 Texas Instruments Inc Dram-zelle und verfahren.
CN1004734B (zh) * 1984-12-07 1989-07-05 得克萨斯仪器公司 动态随机存取存贮器单元(dram)和生产方法
JPS61285752A (ja) * 1985-06-12 1986-12-16 Sanyo Electric Co Ltd 半導体記憶装置
US4649625A (en) * 1985-10-21 1987-03-17 International Business Machines Corporation Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
US4728623A (en) * 1986-10-03 1988-03-01 International Business Machines Corporation Fabrication method for forming a self-aligned contact window and connection in an epitaxial layer and device structures employing the method

Also Published As

Publication number Publication date
JPH0587188B2 (enExample) 1993-12-15
AU2033688A (en) 1989-02-09
US4833516A (en) 1989-05-23
EP0302204A3 (en) 1989-10-11
EP0302204A2 (en) 1989-02-08
BR8803628A (pt) 1989-02-14
CA1289266C (en) 1991-09-17
JPS6445160A (en) 1989-02-17
AU609167B2 (en) 1991-04-26
EP0302204B1 (en) 1993-10-27

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