DE3688030T2 - Bipolare integrierte schaltung mit isolationsstruktur und substratkontakt und verfahren zur herstellung. - Google Patents

Bipolare integrierte schaltung mit isolationsstruktur und substratkontakt und verfahren zur herstellung.

Info

Publication number
DE3688030T2
DE3688030T2 DE8686201651T DE3688030T DE3688030T2 DE 3688030 T2 DE3688030 T2 DE 3688030T2 DE 8686201651 T DE8686201651 T DE 8686201651T DE 3688030 T DE3688030 T DE 3688030T DE 3688030 T2 DE3688030 T2 DE 3688030T2
Authority
DE
Germany
Prior art keywords
production
integrated circuit
insulation structure
substrate contact
bipolar integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE8686201651T
Other languages
English (en)
Other versions
DE3688030D1 (de
Inventor
Oliver Graham Scott
Yuan-Chi Lin Lawrence
Thye Chua Hua
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25118463&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3688030(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3688030D1 publication Critical patent/DE3688030D1/de
Publication of DE3688030T2 publication Critical patent/DE3688030T2/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
DE8686201651T 1985-09-25 1986-09-24 Bipolare integrierte schaltung mit isolationsstruktur und substratkontakt und verfahren zur herstellung. Revoked DE3688030T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/780,062 US4721682A (en) 1985-09-25 1985-09-25 Isolation and substrate connection for a bipolar integrated circuit

Publications (2)

Publication Number Publication Date
DE3688030D1 DE3688030D1 (de) 1993-04-22
DE3688030T2 true DE3688030T2 (de) 1993-06-24

Family

ID=25118463

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686201651T Revoked DE3688030T2 (de) 1985-09-25 1986-09-24 Bipolare integrierte schaltung mit isolationsstruktur und substratkontakt und verfahren zur herstellung.

Country Status (4)

Country Link
US (1) US4721682A (de)
EP (1) EP0216435B1 (de)
JP (1) JP2628988B2 (de)
DE (1) DE3688030T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6384066A (ja) * 1986-09-26 1988-04-14 Semiconductor Res Found 集積化光トリガ・光クエンチ静電誘導サイリスタ及びその製造方法
ATE78121T1 (de) * 1987-05-01 1992-07-15 Digital Equipment Corp Cmos-integrierte schaltung mit substratkontakt an der oberflaeche und verfahren zu ihrer herstellung.
US4912054A (en) * 1987-05-28 1990-03-27 Texas Instruments Incorporated Integrated bipolar-CMOS circuit isolation process for providing different backgate and substrate bias
US5001538A (en) * 1988-12-28 1991-03-19 Synergy Semiconductor Corporation Bipolar sinker structure and process for forming same
JPH05335529A (ja) * 1992-05-28 1993-12-17 Fujitsu Ltd 半導体装置およびその製造方法
JP4817156B2 (ja) * 1999-08-31 2011-11-16 三谷セキサン株式会社 既製杭
US9653447B2 (en) * 2014-09-24 2017-05-16 Nxp B.V. Local interconnect layer enhanced ESD in a bipolar-CMOS-DMOS

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US4137109A (en) * 1976-04-12 1979-01-30 Texas Instruments Incorporated Selective diffusion and etching method for isolation of integrated logic circuit
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4269636A (en) * 1978-12-29 1981-05-26 Harris Corporation Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
JPS588139B2 (ja) * 1979-05-31 1983-02-14 富士通株式会社 半導体装置の製造方法
US4376664A (en) * 1979-05-31 1983-03-15 Fujitsu Limited Method of producing a semiconductor device
JPS5673446A (en) * 1979-11-21 1981-06-18 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS586308B2 (ja) * 1979-12-19 1983-02-03 三菱電機株式会社 半導体装置
JPS5780755A (en) * 1980-11-07 1982-05-20 Mitsubishi Electric Corp Semiconductor device
US4445268A (en) * 1981-02-14 1984-05-01 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor integrated circuit BI-MOS device
JPS5810834A (ja) * 1981-07-10 1983-01-21 Nec Corp 半導体装置
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
JPS5870570A (ja) * 1981-09-28 1983-04-27 Fujitsu Ltd 半導体装置の製造方法
JPS5866359A (ja) * 1981-09-28 1983-04-20 Fujitsu Ltd 半導体装置の製造方法
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
JPS58142542A (ja) * 1982-02-18 1983-08-24 Mitsubishi Electric Corp 誘電体分離構造の半導体集積回路装置の製造方法
JPS58145542A (ja) * 1982-02-25 1983-08-30 Hashimoto Forming Co Ltd モ−ルデイングとその製造方法
JPS59121848A (ja) * 1982-12-28 1984-07-14 Toshiba Corp 半導体装置の製造方法
US4536945A (en) * 1983-11-02 1985-08-27 National Semiconductor Corporation Process for producing CMOS structures with Schottky bipolar transistors
US4584763A (en) * 1983-12-15 1986-04-29 International Business Machines Corporation One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation

Also Published As

Publication number Publication date
EP0216435A3 (en) 1990-07-04
JP2628988B2 (ja) 1997-07-09
US4721682A (en) 1988-01-26
EP0216435A2 (de) 1987-04-01
DE3688030D1 (de) 1993-04-22
EP0216435B1 (de) 1993-03-17
JPS6323335A (ja) 1988-01-30

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8331 Complete revocation