DE3889357T2 - Verfahren zur Herstellung einer integrierten Kundenwunschschaltung mit isoliertem Gate. - Google Patents

Verfahren zur Herstellung einer integrierten Kundenwunschschaltung mit isoliertem Gate.

Info

Publication number
DE3889357T2
DE3889357T2 DE3889357T DE3889357T DE3889357T2 DE 3889357 T2 DE3889357 T2 DE 3889357T2 DE 3889357 T DE3889357 T DE 3889357T DE 3889357 T DE3889357 T DE 3889357T DE 3889357 T2 DE3889357 T2 DE 3889357T2
Authority
DE
Germany
Prior art keywords
production
insulated gate
integrated customer
customer circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3889357T
Other languages
English (en)
Other versions
DE3889357D1 (de
Inventor
Masazumi C O Patent Di Shiochi
Akimitsu Ugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3889357D1 publication Critical patent/DE3889357D1/de
Publication of DE3889357T2 publication Critical patent/DE3889357T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
DE3889357T 1987-02-23 1988-02-22 Verfahren zur Herstellung einer integrierten Kundenwunschschaltung mit isoliertem Gate. Expired - Lifetime DE3889357T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62039599A JPH0758734B2 (ja) 1987-02-23 1987-02-23 絶縁ゲ−ト型セミカスタム集積回路

Publications (2)

Publication Number Publication Date
DE3889357D1 DE3889357D1 (de) 1994-06-09
DE3889357T2 true DE3889357T2 (de) 1994-10-20

Family

ID=12557577

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889357T Expired - Lifetime DE3889357T2 (de) 1987-02-23 1988-02-22 Verfahren zur Herstellung einer integrierten Kundenwunschschaltung mit isoliertem Gate.

Country Status (5)

Country Link
US (1) US4868705A (de)
EP (1) EP0280236B1 (de)
JP (1) JPH0758734B2 (de)
KR (1) KR910001982B1 (de)
DE (1) DE3889357T2 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900001398B1 (ko) * 1987-11-30 1990-03-09 삼성전자 주식회사 양방성 입출력 셀
JPH07105446B2 (ja) * 1988-01-11 1995-11-13 株式会社東芝 Mos型半導体装置の入力保護回路
JPH02113623A (ja) * 1988-10-21 1990-04-25 Sharp Corp 集積回路の静電気保護回路
US5200876A (en) * 1989-04-10 1993-04-06 Matsushita Electric Industrial Co., Ltd. Electrostatic breakdown protection circuit
US5124877A (en) * 1989-07-18 1992-06-23 Gazelle Microcircuits, Inc. Structure for providing electrostatic discharge protection
JP2754072B2 (ja) * 1990-02-07 1998-05-20 三菱電機株式会社 半導体装置の入力回路
DE4004526C1 (de) * 1990-02-14 1991-09-05 Texas Instruments Deutschland Gmbh, 8050 Freising, De
US5229635A (en) * 1991-08-21 1993-07-20 Vlsi Technology, Inc. ESD protection circuit and method for power-down application
US5513064A (en) * 1991-12-13 1996-04-30 Texas Instruments Incorporated Method and device for improving I/O ESD tolerance
GB2273831B (en) * 1992-12-24 1997-03-26 Motorola Semiconducteurs Voltage protection circuit
US5311391A (en) * 1993-05-04 1994-05-10 Hewlett-Packard Company Electrostatic discharge protection circuit with dynamic triggering
US5473500A (en) * 1994-01-13 1995-12-05 Atmel Corporation Electrostatic discharge circuit for high speed, high voltage circuitry
US5532896A (en) * 1994-04-26 1996-07-02 Coussens; Eugene Distributed silicon controlled rectifiers for ESD protection
JPH088391A (ja) * 1994-06-17 1996-01-12 Mitsubishi Electric Corp 半導体回路
JP2834034B2 (ja) * 1995-06-22 1998-12-09 日本電気アイシーマイコンシステム株式会社 半導体装置
US5745323A (en) * 1995-06-30 1998-04-28 Analog Devices, Inc. Electrostatic discharge protection circuit for protecting CMOS transistors on integrated circuit processes
US5729419A (en) * 1995-11-20 1998-03-17 Integrated Device Technology, Inc. Changed device model electrostatic discharge protection circuit for output drivers and method of implementing same
US5751525A (en) * 1996-01-05 1998-05-12 Analog Devices, Inc. EOS/ESD Protection circuit for an integrated circuit with operating/test voltages exceeding power supply rail voltages
US5831312A (en) * 1996-04-09 1998-11-03 United Microelectronics Corporation Electrostic discharge protection device comprising a plurality of trenches
JP3464340B2 (ja) * 1996-04-19 2003-11-10 沖電気工業株式会社 半導体集積回路装置
US5739998A (en) * 1996-07-12 1998-04-14 Kabushiki Kaisha Toshiba Protective circuit and semiconductor integrated circuit incorporating protective circuit
US5917689A (en) * 1996-09-12 1999-06-29 Analog Devices, Inc. General purpose EOS/ESD protection circuit for bipolar-CMOS and CMOS integrated circuits
US5748028A (en) * 1996-10-31 1998-05-05 International Business Machines Corporation Method and apparatus for multi-level input voltage receiver circuit
US5838146A (en) * 1996-11-12 1998-11-17 Analog Devices, Inc. Method and apparatus for providing ESD/EOS protection for IC power supply pins
US5991134A (en) * 1997-06-19 1999-11-23 Advanced Micro Devices, Inc. Switchable ESD protective shunting circuit for semiconductor devices
JP4054093B2 (ja) * 1997-10-09 2008-02-27 株式会社ルネサステクノロジ 半導体装置
US6181193B1 (en) * 1999-10-08 2001-01-30 International Business Machines Corporation Using thick-oxide CMOS devices to interface high voltage integrated circuits
US7333310B2 (en) * 2003-12-18 2008-02-19 Stmicroelectronics, Inc. ESD bonding pad
US20050180071A1 (en) * 2004-02-13 2005-08-18 Yi-Hsun Wu Circuit and method for ESD protection
US20050224883A1 (en) * 2004-04-06 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit design for increasing charge device model immunity
JP5712591B2 (ja) * 2010-12-10 2015-05-07 セイコーエプソン株式会社 集積回路装置、電子機器及び集積回路装置の製造方法
US8941958B2 (en) * 2011-04-22 2015-01-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP5969961B2 (ja) * 2013-07-12 2016-08-17 富士フイルム株式会社 配線基板
US9659924B2 (en) * 2014-05-25 2017-05-23 Mediatek Inc. Signal receiving circuit and signal transceiving circuit
DE102020109476A1 (de) 2020-02-02 2021-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte schaltung
CN113053870A (zh) 2020-02-02 2021-06-29 台湾积体电路制造股份有限公司 集成电路
CN113271089B (zh) * 2021-04-14 2023-04-11 杭州士兰微电子股份有限公司 栅极驱动电路及其智能功率模块
WO2023210631A1 (ja) * 2022-04-27 2023-11-02 ローム株式会社 I/o回路、半導体装置、セルライブラリ、半導体装置の回路設計方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4264941A (en) * 1979-02-14 1981-04-28 National Semiconductor Corporation Protective circuit for insulated gate field effect transistor integrated circuits
US4282556A (en) * 1979-05-21 1981-08-04 Rca Corporation Input protection device for insulated gate field effect transistor
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
US4527213A (en) * 1981-11-27 1985-07-02 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit device with circuits for protecting an input section against an external surge
JPS6027145A (ja) * 1983-07-25 1985-02-12 Hitachi Ltd 半導体集積回路装置
JPS60136241A (ja) * 1983-12-23 1985-07-19 Toshiba Corp ゲ−トアレイの入力回路
JPS60142556A (ja) * 1983-12-28 1985-07-27 Toshiba Corp 入力保護回路
JPS613442A (ja) * 1984-06-15 1986-01-09 Nec Corp 半導体装置
JPS61150232A (ja) * 1984-12-24 1986-07-08 Matsushita Electric Ind Co Ltd 半導体集積回路の入出力回路
US4736271A (en) * 1987-06-23 1988-04-05 Signetics Corporation Protection device utilizing one or more subsurface diodes and associated method of manufacture

Also Published As

Publication number Publication date
JPH0758734B2 (ja) 1995-06-21
EP0280236B1 (de) 1994-05-04
US4868705A (en) 1989-09-19
KR910001982B1 (ko) 1991-03-30
JPS63205928A (ja) 1988-08-25
DE3889357D1 (de) 1994-06-09
KR880010500A (ko) 1988-10-10
EP0280236A2 (de) 1988-08-31
EP0280236A3 (en) 1990-07-25

Similar Documents

Publication Publication Date Title
DE3889357T2 (de) Verfahren zur Herstellung einer integrierten Kundenwunschschaltung mit isoliertem Gate.
DE3686125D1 (de) Verfahren zur herstellung einer integrierten schaltung.
DE3587868D1 (de) Verfahren zur Herstellung von Aerogelen.
DE3587100T2 (de) Verfahren zur herstellung einer auf der halbleiter-auf-isolator-technologie basierenden integrierten schaltung.
DE3852444D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit isoliertem Gatter.
DE3850285T2 (de) Verfahren zur Herstellung von dünnen supraleitenden Schichten.
DE3888003D1 (de) Verfahren zur Herstellung keramischer Supraleiter.
DE3867670D1 (de) Verfahren zur herstellung einer halbleiteranordnung vom feldeffekttransistor-typ.
DE68916393T2 (de) Verfahren zur Herstellung von ebenen Wafern.
DE69004932T2 (de) Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen.
DE3789680D1 (de) Verfahren zur Herstellung von Halbleiterbauelementen.
DE3688757T2 (de) Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen.
DE3881091T2 (de) Verfahren zur herstellung von phosphatidsaeurederivaten.
DE58907207D1 (de) Verfahren zur Herstellung von metallischen Schichten.
DE58906122D1 (de) Verfahren zur Herstellung von Phenylethanolen.
DE3884577T2 (de) Verfahren zur Herstellung von Polyolefinen.
DE3788412D1 (de) Verfahren zur Herstellung synthetischen Mazzits.
DE3862774D1 (de) Verfahren zur herstellung von vinylphosphonsaeuredialkylestern.
DE3850151D1 (de) Verfahren zur Herstellung von Mustern.
DE59009201D1 (de) Verfahren zur Herstellung elektrisch leitfähiger Polyheteroaromaten.
DE3870746D1 (de) Verfahren zur herstellung von benzoesaeurederivaten.
DE3880902D1 (de) Verfahren zur herstellung von hydroxybenzoesaeure.
ATE85321T1 (de) Verfahren zur herstellung von anilinofumaraten.
DE69018539D1 (de) Verfahren zur Herstellung von supraleitenden Dünnschichten.
DE3881589T2 (de) Verfahren zur Herstellung supraleitender Kupferoxid-Schichten.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition