DE3280101D1 - Integrierte schaltungsanordnungen mit dielektrischen isolationsmassen und verfahren zur herstellung dieser anordnungen. - Google Patents

Integrierte schaltungsanordnungen mit dielektrischen isolationsmassen und verfahren zur herstellung dieser anordnungen.

Info

Publication number
DE3280101D1
DE3280101D1 DE8282108596T DE3280101T DE3280101D1 DE 3280101 D1 DE3280101 D1 DE 3280101D1 DE 8282108596 T DE8282108596 T DE 8282108596T DE 3280101 T DE3280101 T DE 3280101T DE 3280101 D1 DE3280101 D1 DE 3280101D1
Authority
DE
Germany
Prior art keywords
arrangements
producing
integrated circuit
dielectric insulation
insulation dimensions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8282108596T
Other languages
English (en)
Inventor
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14654781A external-priority patent/JPS5848437A/ja
Priority claimed from JP16131281A external-priority patent/JPS5861642A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3280101D1 publication Critical patent/DE3280101D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
DE8282108596T 1981-09-17 1982-09-17 Integrierte schaltungsanordnungen mit dielektrischen isolationsmassen und verfahren zur herstellung dieser anordnungen. Expired - Lifetime DE3280101D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP14654781A JPS5848437A (ja) 1981-09-17 1981-09-17 半導体装置の製造方法
JP16131281A JPS5861642A (ja) 1981-10-09 1981-10-09 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
DE3280101D1 true DE3280101D1 (de) 1990-03-08

Family

ID=26477357

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282108596T Expired - Lifetime DE3280101D1 (de) 1981-09-17 1982-09-17 Integrierte schaltungsanordnungen mit dielektrischen isolationsmassen und verfahren zur herstellung dieser anordnungen.

Country Status (3)

Country Link
US (1) US4491486A (de)
EP (1) EP0091984B1 (de)
DE (1) DE3280101D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4753901A (en) * 1985-11-15 1988-06-28 Ncr Corporation Two mask technique for planarized trench oxide isolation of integrated devices
JP3157357B2 (ja) * 1993-06-14 2001-04-16 株式会社東芝 半導体装置
US5575878A (en) * 1994-11-30 1996-11-19 Honeywell Inc. Method for making surface relief profilers
KR100236097B1 (ko) * 1996-10-30 1999-12-15 김영환 반도체 장치의 격리막 형성방법
US6200880B1 (en) * 1998-11-16 2001-03-13 United Microelectronics Corp. Method for forming shallow trench isolation
JP2000206348A (ja) 1999-01-13 2000-07-28 Furukawa Electric Co Ltd:The 光導波路回路の光透過波長の補償方法
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
TWI401749B (zh) * 2004-12-27 2013-07-11 Third Dimension 3D Sc Inc 用於高電壓超接面終止之方法
US7439583B2 (en) * 2004-12-27 2008-10-21 Third Dimension (3D) Semiconductor, Inc. Tungsten plug drain extension
US20090026586A1 (en) * 2005-04-22 2009-01-29 Icemos Technology Corporation Superjunction Device Having Oxide Lined Trenches and Method for Manufacturing a Superjunction Device Having Oxide Lined Trenches
US7446018B2 (en) * 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
US7429772B2 (en) * 2006-04-27 2008-09-30 Icemos Technology Corporation Technique for stable processing of thin/fragile substrates
US7723172B2 (en) * 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US8580651B2 (en) * 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US20080272429A1 (en) * 2007-05-04 2008-11-06 Icemos Technology Corporation Superjunction devices having narrow surface layout of terminal structures and methods of manufacturing the devices
DE102007035251B3 (de) * 2007-07-27 2008-08-28 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von Isolationsgräben mit unterschiedlichen Seitenwanddotierungen
US8012806B2 (en) * 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices
US8159039B2 (en) * 2008-01-11 2012-04-17 Icemos Technology Ltd. Superjunction device having a dielectric termination and methods for manufacturing the device
US7795045B2 (en) * 2008-02-13 2010-09-14 Icemos Technology Ltd. Trench depth monitor for semiconductor manufacturing
US7846821B2 (en) * 2008-02-13 2010-12-07 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US8030133B2 (en) 2008-03-28 2011-10-04 Icemos Technology Ltd. Method of fabricating a bonded wafer substrate for use in MEMS structures
US8946814B2 (en) 2012-04-05 2015-02-03 Icemos Technology Ltd. Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates
US9576842B2 (en) 2012-12-10 2017-02-21 Icemos Technology, Ltd. Grass removal in patterned cavity etching

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972751A (en) * 1973-07-17 1976-08-03 Owego Heat Treat, Inc. Method of heat treating ferrous workpieces
US3966577A (en) * 1973-08-27 1976-06-29 Trw Inc. Dielectrically isolated semiconductor devices
JPS5131186A (de) * 1974-09-11 1976-03-17 Hitachi Ltd
JPS5347253B2 (de) * 1974-10-16 1978-12-20
US4032373A (en) * 1975-10-01 1977-06-28 Ncr Corporation Method of manufacturing dielectrically isolated semiconductive device
NL178487C (nl) * 1976-03-26 1986-04-01 Stamicarbon Inrichting en werkwijze voor het versproeien van een vloeistof.
US4044452A (en) * 1976-10-06 1977-08-30 International Business Machines Corporation Process for making field effect and bipolar transistors on the same semiconductor chip
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4139442A (en) * 1977-09-13 1979-02-13 International Business Machines Corporation Reactive ion etching method for producing deep dielectric isolation in silicon
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4209380A (en) * 1978-07-27 1980-06-24 Ppg Industries, Inc. Cathode element for electrolytic cell
DE2949360A1 (de) * 1978-12-08 1980-06-26 Hitachi Ltd Verfahren zur herstellung einer oxidierten isolation fuer integrierte schaltungen
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
US4211582A (en) * 1979-06-28 1980-07-08 International Business Machines Corporation Process for making large area isolation trenches utilizing a two-step selective etching technique
JPS5636143A (en) * 1979-08-31 1981-04-09 Hitachi Ltd Manufacture of semiconductor device
US4338138A (en) * 1980-03-03 1982-07-06 International Business Machines Corporation Process for fabricating a bipolar transistor
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
US4378630A (en) * 1980-05-05 1983-04-05 International Business Machines Corporation Process for fabricating a high performance PNP and NPN structure
US4390393A (en) * 1981-11-12 1983-06-28 General Electric Company Method of forming an isolation trench in a semiconductor substrate
JPS58165341A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0091984A2 (de) 1983-10-26
EP0091984B1 (de) 1990-01-31
EP0091984A3 (en) 1986-08-20
US4491486A (en) 1985-01-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee