ATE78121T1 - Cmos-integrierte schaltung mit substratkontakt an der oberflaeche und verfahren zu ihrer herstellung. - Google Patents

Cmos-integrierte schaltung mit substratkontakt an der oberflaeche und verfahren zu ihrer herstellung.

Info

Publication number
ATE78121T1
ATE78121T1 AT88400836T AT88400836T ATE78121T1 AT E78121 T1 ATE78121 T1 AT E78121T1 AT 88400836 T AT88400836 T AT 88400836T AT 88400836 T AT88400836 T AT 88400836T AT E78121 T1 ATE78121 T1 AT E78121T1
Authority
AT
Austria
Prior art keywords
integrated circuit
cmos
substrate contact
production
substrate
Prior art date
Application number
AT88400836T
Other languages
English (en)
Inventor
Gregory J Grula
Andre I Nasr
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21938912&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE78121(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE78121T1 publication Critical patent/ATE78121T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6349—Deposition of epitaxial materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Element Separation (AREA)
AT88400836T 1987-05-01 1988-04-07 Cmos-integrierte schaltung mit substratkontakt an der oberflaeche und verfahren zu ihrer herstellung. ATE78121T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US4561087A 1987-05-01 1987-05-01
EP88400836A EP0290305B1 (de) 1987-05-01 1988-04-07 CMOS-integrierte Schaltung mit Substratkontakt an der Oberfläche und Verfahren zu ihrer Herstellung

Publications (1)

Publication Number Publication Date
ATE78121T1 true ATE78121T1 (de) 1992-07-15

Family

ID=21938912

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88400836T ATE78121T1 (de) 1987-05-01 1988-04-07 Cmos-integrierte schaltung mit substratkontakt an der oberflaeche und verfahren zu ihrer herstellung.

Country Status (10)

Country Link
EP (1) EP0290305B1 (de)
JP (2) JPS6428861A (de)
KR (1) KR930011468B1 (de)
CN (1) CN1019434B (de)
AT (1) ATE78121T1 (de)
AU (1) AU605853B2 (de)
BR (1) BR8802165A (de)
CA (1) CA1315020C (de)
DE (1) DE3872590T2 (de)
MX (1) MX168378B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU617779B2 (en) * 1988-03-30 1991-12-05 Unisearch Limited Improved method of manufacturing buried contact solar cells
US5361842A (en) * 1993-05-27 1994-11-08 Shell Oil Company Drilling and cementing with blast furnace slag/silicate fluid
US5337824A (en) * 1993-06-28 1994-08-16 Shell Oil Company Coal slag universal fluid
EP2457978A1 (de) 2010-11-24 2012-05-30 Evonik Degussa GmbH Verfahren zur Pyrolyse von ligninreicher Biomasse, damit hergestellte kohlenstoffreiche Feststoffe und Verwendung davon als Bodenverbesserungsmittel oder Adsorptionsmittel

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5673446A (en) * 1979-11-21 1981-06-18 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
JPS58218158A (ja) * 1982-06-11 1983-12-19 Toshiba Corp 相補型ｍｏｓ半導体装置
JPS60128655A (ja) * 1983-12-16 1985-07-09 Hitachi Ltd 半導体装置
JPH0770604B2 (ja) * 1985-04-17 1995-07-31 ソニー株式会社 相補型電界効果トランジスタの製法
US4721682A (en) * 1985-09-25 1988-01-26 Monolithic Memories, Inc. Isolation and substrate connection for a bipolar integrated circuit

Also Published As

Publication number Publication date
DE3872590D1 (de) 1992-08-13
EP0290305A1 (de) 1988-11-09
BR8802165A (pt) 1988-12-06
DE3872590T2 (de) 1993-03-11
JPS6428861A (en) 1989-01-31
CA1315020C (en) 1993-03-23
KR930011468B1 (ko) 1993-12-08
MX168378B (es) 1993-05-20
JPS6448454A (en) 1989-02-22
KR880014690A (ko) 1988-12-24
AU1466688A (en) 1988-11-03
AU605853B2 (en) 1991-01-24
CN1019434B (zh) 1992-12-09
CN1031155A (zh) 1989-02-15
EP0290305B1 (de) 1992-07-08

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Legal Events

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