DE3667361D1 - Verfahren zum herstellen eines metallischen verbindungsmusters fuer hochintegrierte schaltungsbauelemente. - Google Patents

Verfahren zum herstellen eines metallischen verbindungsmusters fuer hochintegrierte schaltungsbauelemente.

Info

Publication number
DE3667361D1
DE3667361D1 DE8686402138T DE3667361T DE3667361D1 DE 3667361 D1 DE3667361 D1 DE 3667361D1 DE 8686402138 T DE8686402138 T DE 8686402138T DE 3667361 T DE3667361 T DE 3667361T DE 3667361 D1 DE3667361 D1 DE 3667361D1
Authority
DE
Germany
Prior art keywords
producing
integrated circuit
circuit components
highly integrated
connection pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686402138T
Other languages
English (en)
Inventor
Pierre Residence Le Ch Merenda
Daniel Lambert
Philippe Chantraine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE3667361D1 publication Critical patent/DE3667361D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)
DE8686402138T 1985-10-03 1986-10-01 Verfahren zum herstellen eines metallischen verbindungsmusters fuer hochintegrierte schaltungsbauelemente. Expired - Fee Related DE3667361D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8514670A FR2588418B1 (fr) 1985-10-03 1985-10-03 Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant

Publications (1)

Publication Number Publication Date
DE3667361D1 true DE3667361D1 (de) 1990-01-11

Family

ID=9323499

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686402138T Expired - Fee Related DE3667361D1 (de) 1985-10-03 1986-10-01 Verfahren zum herstellen eines metallischen verbindungsmusters fuer hochintegrierte schaltungsbauelemente.

Country Status (5)

Country Link
US (1) US4826786A (de)
EP (1) EP0221798B1 (de)
JP (1) JPS62176147A (de)
DE (1) DE3667361D1 (de)
FR (1) FR2588418B1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994402A (en) * 1987-06-26 1991-02-19 Hewlett-Packard Company Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device
JPH063804B2 (ja) * 1988-01-21 1994-01-12 シャープ株式会社 半導体装置製造方法
US4986878A (en) * 1988-07-19 1991-01-22 Cypress Semiconductor Corp. Process for improved planarization of the passivation layers for semiconductor devices
JPH02237135A (ja) * 1989-03-10 1990-09-19 Fujitsu Ltd 半導体装置の製造方法
US4988405A (en) * 1989-12-21 1991-01-29 At&T Bell Laboratories Fabrication of devices utilizing a wet etchback procedure
JP2518435B2 (ja) * 1990-01-29 1996-07-24 ヤマハ株式会社 多層配線形成法
US5250468A (en) * 1990-02-05 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including interlaying insulating film
US5132774A (en) * 1990-02-05 1992-07-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including interlayer insulating film
US5245213A (en) * 1991-10-10 1993-09-14 Sgs-Thomson Microelectronics, Inc. Planarized semiconductor product
US5576225A (en) * 1992-05-09 1996-11-19 Semiconductor Energy Laboratory Co., Ltd. Method of forming electric circuit using anodic oxidation
US5250472A (en) * 1992-09-03 1993-10-05 Industrial Technology Research Institute Spin-on-glass integration planarization having siloxane partial etchback and silicate processes
US5264386A (en) * 1992-09-08 1993-11-23 United Microelectronics Corporation Read only memory manufacturing method
US5312512A (en) * 1992-10-23 1994-05-17 Ncr Corporation Global planarization using SOG and CMP
JPH06302599A (ja) * 1993-04-13 1994-10-28 Toshiba Corp 半導体装置およびその製造方法
US5486493A (en) * 1994-02-25 1996-01-23 Jeng; Shin-Puu Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
US5461010A (en) * 1994-06-13 1995-10-24 Industrial Technology Research Institute Two step etch back spin-on-glass process for semiconductor planarization
DE4434891B4 (de) * 1994-09-29 2005-01-05 Infineon Technologies Ag Verfahren zum Freilegen einer oberen Stegfläche eines auf der Oberfläche eines Substrats ausgebildeten und mit einem Material umformten schmalen Steges im Mikrometerbereich und Anwendung eines solchen Verfahrens zur Kontaktierung schmaler Stege
US5856707A (en) * 1995-09-11 1999-01-05 Stmicroelectronics, Inc. Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed
US5665657A (en) * 1995-09-18 1997-09-09 Taiwan Semiconductor Manufacturing Company, Ltd Spin-on-glass partial etchback planarization process
US6204107B1 (en) * 1998-12-08 2001-03-20 United Microelectronics Corp. Method for forming multi-layered liner on sidewall of node contact opening

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3506880A (en) * 1963-06-28 1970-04-14 Ibm Semiconductor device
FR1542658A (fr) * 1966-09-30 Ibm Technique de formation de verre photosensible pour faire des trous de contact dans des couches de verre de protection
JPS5849026B2 (ja) * 1976-06-23 1983-11-01 株式会社日立製作所 多層配線の製法
JPS5621332A (en) * 1979-07-31 1981-02-27 Fujitsu Ltd Manufacture of semiconductor device
US4222792A (en) * 1979-09-10 1980-09-16 International Business Machines Corporation Planar deep oxide isolation process utilizing resin glass and E-beam exposure
JPS57177558A (en) * 1981-04-24 1982-11-01 Fujitsu Ltd Semiconductor device and manufacture thereof
US4492717A (en) * 1981-07-27 1985-01-08 International Business Machines Corporation Method for forming a planarized integrated circuit
CA1169022A (en) * 1982-04-19 1984-06-12 Kevin Duncan Integrated circuit planarizing process
JPS58184741A (ja) * 1982-04-23 1983-10-28 Toshiba Corp 半導体装置の製造方法
JPS58197827A (ja) * 1982-05-14 1983-11-17 Toshiba Corp 半導体装置の製造方法
JPS5966147A (ja) * 1982-10-08 1984-04-14 Hitachi Ltd 多層配線の製造方法
JPS59169151A (ja) * 1983-03-17 1984-09-25 Toshiba Corp 半導体装置の製造方法
JPS59215747A (ja) * 1983-05-24 1984-12-05 Nec Corp 半導体装置の製造方法
JPS60138940A (ja) * 1983-12-27 1985-07-23 Toshiba Corp 半導体装置の製造方法
JPS61116858A (ja) * 1984-10-24 1986-06-04 Fujitsu Ltd 層間絶縁膜の形成方法
US4654113A (en) * 1984-02-10 1987-03-31 Fujitsu Limited Process for fabricating a semiconductor device
US4481070A (en) * 1984-04-04 1984-11-06 Advanced Micro Devices, Inc. Double planarization process for multilayer metallization of integrated circuit structures
US4519872A (en) * 1984-06-11 1985-05-28 International Business Machines Corporation Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes
US4541169A (en) * 1984-10-29 1985-09-17 International Business Machines Corporation Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip
JPS61180458A (ja) * 1985-02-05 1986-08-13 Nec Corp 半導体装置の製造方法
US4662064A (en) * 1985-08-05 1987-05-05 Rca Corporation Method of forming multi-level metallization
FR2588417B1 (fr) * 1985-10-03 1988-07-29 Bull Sa Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant

Also Published As

Publication number Publication date
JPS62176147A (ja) 1987-08-01
US4826786A (en) 1989-05-02
EP0221798B1 (de) 1989-12-06
FR2588418A1 (fr) 1987-04-10
EP0221798A1 (de) 1987-05-13
FR2588418B1 (fr) 1988-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee