DE3578729D1 - Verfahren zur bildung eines leitermusters. - Google Patents

Verfahren zur bildung eines leitermusters.

Info

Publication number
DE3578729D1
DE3578729D1 DE8585113017T DE3578729T DE3578729D1 DE 3578729 D1 DE3578729 D1 DE 3578729D1 DE 8585113017 T DE8585113017 T DE 8585113017T DE 3578729 T DE3578729 T DE 3578729T DE 3578729 D1 DE3578729 D1 DE 3578729D1
Authority
DE
Germany
Prior art keywords
forming
ladder pattern
ladder
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585113017T
Other languages
English (en)
Inventor
Yoshihiro Kishita
Motoki Furukawa
Tatsuro Mitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP21631784A external-priority patent/JPS6196735A/ja
Priority claimed from JP21631684A external-priority patent/JPS6196765A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3578729D1 publication Critical patent/DE3578729D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Drying Of Semiconductors (AREA)
DE8585113017T 1984-10-17 1985-10-14 Verfahren zur bildung eines leitermusters. Expired - Lifetime DE3578729D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21631784A JPS6196735A (ja) 1984-10-17 1984-10-17 導体パタ−ン形成方法
JP21631684A JPS6196765A (ja) 1984-10-17 1984-10-17 金属パタ−ン形成方法

Publications (1)

Publication Number Publication Date
DE3578729D1 true DE3578729D1 (de) 1990-08-23

Family

ID=26521361

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585113017T Expired - Lifetime DE3578729D1 (de) 1984-10-17 1985-10-14 Verfahren zur bildung eines leitermusters.

Country Status (3)

Country Link
US (1) US4674174A (de)
EP (1) EP0178619B1 (de)
DE (1) DE3578729D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821085A (en) * 1985-05-01 1989-04-11 Texas Instruments Incorporated VLSI local interconnect structure
US4811078A (en) * 1985-05-01 1989-03-07 Texas Instruments Incorporated Integrated circuit device and process with tin capacitors
US4814854A (en) * 1985-05-01 1989-03-21 Texas Instruments Incorporated Integrated circuit device and process with tin-gate transistor
US4956308A (en) * 1987-01-20 1990-09-11 Itt Corporation Method of making self-aligned field-effect transistor
US4782032A (en) * 1987-01-12 1988-11-01 Itt Gallium Arsenide Technology Center, A Division Of Itt Corporation Method of making self-aligned GaAs devices having TiWNx gate/interconnect
US5027166A (en) * 1987-12-04 1991-06-25 Sanken Electric Co., Ltd. High voltage, high speed Schottky semiconductor device and method of fabrication
US5025303A (en) * 1988-02-26 1991-06-18 Texas Instruments Incorporated Product of pillar alignment and formation process
US4935805A (en) * 1988-05-16 1990-06-19 Eaton Corporation T-type undercut electrical contact on a semiconductor substrate
US4923827A (en) * 1988-05-16 1990-05-08 Eaton Corporation T-type undercut electrical contact process on a semiconductor substrate
JP2606900B2 (ja) * 1988-09-08 1997-05-07 株式会社東芝 パターン形成方法
US5153754A (en) * 1989-06-30 1992-10-06 General Electric Company Multi-layer address lines for amorphous silicon liquid crystal display devices
GB2237929A (en) * 1989-10-23 1991-05-15 Philips Electronic Associated A method of manufacturing a semiconductor device
DE69128123T2 (de) * 1990-08-31 1998-03-05 Texas Instruments Inc Verfahren zum Herstellen selbst-ausrichtender bipolarer Transistoren mit Heteroübergang
US5182218A (en) * 1991-02-25 1993-01-26 Sumitomo Electric Industries, Ltd. Production methods for compound semiconductor device having lightly doped drain structure
US5176792A (en) * 1991-10-28 1993-01-05 At&T Bell Laboratories Method for forming patterned tungsten layers
FR2686734B1 (fr) * 1992-01-24 1994-03-11 Thomson Composants Microondes Procede de realisation d'un transistor.
US5536666A (en) * 1994-06-03 1996-07-16 Itt Corporation Method for fabricating a planar ion-implanted GaAs MESFET with improved open-channel burnout characteristics
KR19980060606A (ko) * 1996-12-31 1998-10-07 김영환 반도체 소자의 금속배선 형성 방법
US6420099B1 (en) * 1999-08-02 2002-07-16 Infineon Technologies Ag Tungsten hard mask for dry etching aluminum-containing layers
JP2004071015A (ja) * 2002-08-05 2004-03-04 Fujitsu Ltd 薄膜磁気ヘッドの製造方法
NL1026013C2 (nl) 2004-04-23 2005-10-25 Otb Group Bv Werkwijze en inrichting voor het nauwkeurig aanbrengen van structuren op een substraat.
WO2010010176A1 (fr) * 2008-07-25 2010-01-28 Commissariat A L'energie Atomique Procede de microstructuration d'une couche de diamant
US9917027B2 (en) * 2015-12-30 2018-03-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with aluminum via structures and methods for fabricating the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1954499A1 (de) * 1969-10-29 1971-05-06 Siemens Ag Verfahren zur Herstellung von Halbleiterschaltkreisen mit Leitbahnen
US4132586A (en) * 1977-12-20 1979-01-02 International Business Machines Corporation Selective dry etching of substrates
US4362597A (en) * 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
CA1200624A (en) * 1981-08-10 1986-02-11 Susumu Muramoto Method for the manufacture of semiconductor device using refractory metal in a lift-off step
US4400257A (en) * 1982-12-21 1983-08-23 Rca Corporation Method of forming metal lines
US4586063A (en) * 1984-04-02 1986-04-29 Oki Electric Industry Co., Ltd. Schottky barrier gate FET including tungsten-aluminum alloy

Also Published As

Publication number Publication date
EP0178619A3 (en) 1988-09-14
US4674174A (en) 1987-06-23
EP0178619B1 (de) 1990-07-18
EP0178619A2 (de) 1986-04-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee