DE68927531D1 - Verfahren zum Herstellen einer Leiterplatte - Google Patents

Verfahren zum Herstellen einer Leiterplatte

Info

Publication number
DE68927531D1
DE68927531D1 DE68927531T DE68927531T DE68927531D1 DE 68927531 D1 DE68927531 D1 DE 68927531D1 DE 68927531 T DE68927531 T DE 68927531T DE 68927531 T DE68927531 T DE 68927531T DE 68927531 D1 DE68927531 D1 DE 68927531D1
Authority
DE
Germany
Prior art keywords
making
circuit board
printed circuit
printed
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE68927531T
Other languages
English (en)
Other versions
DE68927531T2 (de
Inventor
Tadashi Intellectual Pr Tanaka
Kazuo Intellectual P Matsumura
Hiroshi Intellectual Komorita
Nobuyuki Intellectual Mizunoya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=14307088&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE68927531(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68927531D1 publication Critical patent/DE68927531D1/de
Application granted granted Critical
Publication of DE68927531T2 publication Critical patent/DE68927531T2/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B3/00—Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties
    • H01B3/02—Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties mainly consisting of inorganic substances
    • H01B3/12—Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties mainly consisting of inorganic substances ceramics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
    • H01B5/14—Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12472—Microscopic interfacial wave or roughness
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12993—Surface feature [e.g., rough, mirror]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Ceramic Products (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)
  • Non-Insulated Conductors (AREA)
DE68927531T 1988-04-25 1989-04-21 Verfahren zum Herstellen einer Leiterplatte Revoked DE68927531T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63101681A JPH01272183A (ja) 1988-04-25 1988-04-25 セラミックス回路基板

Publications (2)

Publication Number Publication Date
DE68927531D1 true DE68927531D1 (de) 1997-01-23
DE68927531T2 DE68927531T2 (de) 1997-05-15

Family

ID=14307088

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927531T Revoked DE68927531T2 (de) 1988-04-25 1989-04-21 Verfahren zum Herstellen einer Leiterplatte

Country Status (5)

Country Link
US (2) US4959507A (de)
EP (2) EP0681322A3 (de)
JP (1) JPH01272183A (de)
KR (1) KR910004923B1 (de)
DE (1) DE68927531T2 (de)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2801732B2 (ja) * 1990-03-22 1998-09-21 株式会社東芝 基板配線用クラッド材およびその製造方法
DE4123911C1 (de) * 1991-07-18 1993-01-14 Doduco Gmbh + Co Dr. Eugen Duerrwaechter, 7530 Pforzheim, De
US5220197A (en) * 1991-07-22 1993-06-15 Silicon Power Corporation Single inline packaged solid state relay with high current density capability
US5134094A (en) * 1991-07-22 1992-07-28 Silicon Power Corporation Single inline packaged solid state relay with high current density capability
DE69233801D1 (de) * 1991-07-24 2011-02-17 Denki Kagaku Kogyo Kk Verfahren zur Herstellung eines Schaltungssubstrates mit einem montierten Halbleiterelement
JPH05166969A (ja) * 1991-10-14 1993-07-02 Fuji Electric Co Ltd 半導体装置
US5242535A (en) * 1992-09-29 1993-09-07 The Boc Group, Inc. Method of forming a copper circuit pattern
US5777259A (en) * 1994-01-14 1998-07-07 Brush Wellman Inc. Heat exchanger assembly and method for making the same
CA2140311A1 (en) * 1994-01-14 1995-07-15 Joseph P. Mennucci Multilayer laminate product and process
JP3575068B2 (ja) * 1994-08-02 2004-10-06 住友電気工業株式会社 平滑なめっき層を有するセラミックスメタライズ基板およびその製造方法
US5601675A (en) * 1994-12-06 1997-02-11 International Business Machines Corporation Reworkable electronic apparatus having a fusible layer for adhesively attached components, and method therefor
KR100232660B1 (ko) * 1995-03-20 1999-12-01 니시무로 타이죠 질화규소 회로기판
US6022426A (en) * 1995-05-31 2000-02-08 Brush Wellman Inc. Multilayer laminate process
JP3890539B2 (ja) * 1996-04-12 2007-03-07 Ｄｏｗａホールディングス株式会社 セラミックス−金属複合回路基板
TW353220B (en) 1996-08-20 1999-02-21 Toshiba Corp Silicon nitride circuit board and semiconductor module
US6323549B1 (en) * 1996-08-29 2001-11-27 L. Pierre deRochemont Ceramic composite wiring structures for semiconductor devices and method of manufacture
US5707715A (en) * 1996-08-29 1998-01-13 L. Pierre deRochemont Metal ceramic composites with improved interfacial properties and methods to make such composites
US6143432A (en) * 1998-01-09 2000-11-07 L. Pierre deRochemont Ceramic composites with improved interfacial properties and methods to make such composites
US6207221B1 (en) * 1997-03-01 2001-03-27 Jürgen Schulz-Harder Process for producing a metal-ceramic substrate and a metal-ceramic substrate
US7000316B2 (en) * 1999-09-15 2006-02-21 Curamik Electronics Gmbh Conductor board and method for producing a conductor board
JP4756200B2 (ja) * 2000-09-04 2011-08-24 Ｄｏｗａメタルテック株式会社 金属セラミックス回路基板
FR2814279B1 (fr) * 2000-09-15 2003-02-28 Alstom Substrat pour circuit electronique et module electronique utilisant un tel substrat
FR2814280B1 (fr) * 2000-09-15 2003-05-02 Alstom Substrat pour circuit electronique de puissance et module electronique de puissance utilisant un tel substrat
EP1239515B1 (de) * 2001-03-08 2019-01-02 ALSTOM Transport Technologies Substrat für elektronische Leistungsschaltung und elektronisches Leistungsmodul mit diesem
US6727585B2 (en) * 2001-05-04 2004-04-27 Ixys Corporation Power device with a plastic molded package and direct bonded substrate
US7145254B2 (en) * 2001-07-26 2006-12-05 Denso Corporation Transfer-molded power device and method for manufacturing transfer-molded power device
US8123927B1 (en) * 2003-09-23 2012-02-28 Rockstar Bidco, LP Reduced circuit trace roughness for improved signal performance
JP2007189112A (ja) * 2006-01-16 2007-07-26 Denki Kagaku Kogyo Kk 窒化珪素基板およびそれを用いた回路基板、モジュール。
KR100990288B1 (ko) * 2008-01-25 2010-10-26 엘에스엠트론 주식회사 연성 동박 적층판
KR101289803B1 (ko) * 2008-05-16 2013-07-26 삼성테크윈 주식회사 회로 기판 및 그 제조 방법
JP2011097038A (ja) * 2009-10-02 2011-05-12 Ibiden Co Ltd セラミック配線基板およびその製造方法
EP2683777A2 (de) * 2011-03-08 2014-01-15 Merck Patent GmbH Aluminiumoxid basierte metallisierungsbarriere
DE102012102611B4 (de) * 2012-02-15 2017-07-27 Rogers Germany Gmbh Metall-Keramik-Substrat sowie Verfahren zum Herstellen eines Metall-Keramik-Substrates
JP6028352B2 (ja) * 2012-03-16 2016-11-16 三菱マテリアル株式会社 ヒートシンク付パワーモジュール用基板の製造方法
WO2013184785A1 (en) * 2012-06-05 2013-12-12 Applied Nanotech Holdings, Inc. Pore sealing pastes for porous materials
KR101901890B1 (ko) * 2012-09-28 2018-09-28 엘지이노텍 주식회사 발광 장치
DE102016203030A1 (de) * 2016-02-26 2017-08-31 Heraeus Deutschland GmbH & Co. KG Kupfer-Keramik-Verbund
WO2018180965A1 (ja) * 2017-03-30 2018-10-04 株式会社 東芝 セラミックス銅回路基板およびそれを用いた半導体装置
US10362684B1 (en) * 2018-10-11 2019-07-23 National Chung-Shan Institute Of Science And Technology Method for improving adhesion between ceramic carrier and thick film circuit
WO2021187201A1 (ja) * 2020-03-18 2021-09-23 株式会社 東芝 接合体、セラミックス銅回路基板、接合体の製造方法、およびセラミックス銅回路基板の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3716759A (en) 1970-10-12 1973-02-13 Gen Electric Electronic device with thermally conductive dielectric barrier
US4472762A (en) * 1980-09-25 1984-09-18 Texas Instruments Incorporated Electronic circuit interconnection system
US4490457A (en) * 1980-11-28 1984-12-25 Honeywell Inc. Cold/dry substrate treatment technique which improves photolithographic limits of resolution and exposure tolerance
US4409278A (en) 1981-04-16 1983-10-11 General Electric Company Blister-free direct bonding of metals to ceramics and metals
JPS57188859A (en) * 1981-05-18 1982-11-19 Seiko Epson Corp Metal foil for flexible tape of film carrier
GB2099742B (en) 1981-06-05 1985-07-31 Philips Electronic Associated Bonding metals to non-metals
JPS5842262A (ja) * 1981-09-07 1983-03-11 Toshiba Corp 混成集積回路のリ−ド線接続方法
JPS60173900A (ja) * 1984-02-20 1985-09-07 株式会社東芝 セラミツクス回路基板
US4628598A (en) * 1984-10-02 1986-12-16 The United States Of America As Represented By The Secretary Of The Air Force Mechanical locking between multi-layer printed wiring board conductors and through-hole plating
EP0218022B1 (de) * 1985-08-14 1992-07-29 OMRON Corporation Montagestruktur für einen oberflächenmontierten Bauelementtyp und Verfahren zum Montieren dieses Bauelementtyps auf einer Leiterplatte
JPS6272576A (ja) * 1985-09-26 1987-04-03 株式会社東芝 セラミツクス−金属接合体
JPS62187035A (ja) * 1986-02-12 1987-08-15 日立化成工業株式会社 セラミツクコ−ト積層板の製造方法
JPS62216251A (ja) * 1986-03-17 1987-09-22 Toshiba Corp 高熱伝導性基板
US4767049A (en) * 1986-05-19 1988-08-30 Olin Corporation Special surfaces for wire bonding
JPS63166774A (ja) * 1986-12-27 1988-07-09 同和鉱業株式会社 銅板とアルミナ基板との接合体の製造方法

Also Published As

Publication number Publication date
US4987677A (en) 1991-01-29
JPH01272183A (ja) 1989-10-31
EP0681322A2 (de) 1995-11-08
EP0681322A3 (de) 1998-01-21
US4959507A (en) 1990-09-25
EP0339881A1 (de) 1989-11-02
KR890016585A (ko) 1989-11-29
EP0339881B1 (de) 1996-12-11
DE68927531T2 (de) 1997-05-15
KR910004923B1 (ko) 1991-07-18

Similar Documents

Publication Publication Date Title
DE68927531D1 (de) Verfahren zum Herstellen einer Leiterplatte
DE69024594D1 (de) Verfahren zum Verbinden von Leiterplatten
DE69032793D1 (de) Verfahren zum Herstellen einer Karte
DE68926055D1 (de) Herstellungsverfahren einer mehrschichtigen Leiterplatte
KR890016886A (ko) 인쇄 회로판의 제조방법
DE69122436D1 (de) Verfahren zum Herstellen einer Stufe in einer integrierten Schaltung
DE69027006D1 (de) Verfahren zur Herstellung einer gedruckten Mehrschichtleiterplatte
DE3483003D1 (de) Verfahren zur herstellung einer gedruckten leiterplatte.
KR890700855A (ko) 인쇄 배선 기판용 레지스트 패터닝 방법
GB9113916D0 (en) Method of manufacturing a printed wiring board
EP0552532A3 (en) A method of testing printed circuit boards
EP0231795A3 (en) Method for making printed circuit boards
AR231783A1 (es) Metodo de produccion de placas de circuitos impresos de una configuracion deseada
DE69115852D1 (de) Verfahren zur Herstellung einer Leiterplatte
GB2246480B (en) A method of manufacturing a printed circuit board
DE68920383D1 (de) Verfahren zur Herstellung einer gedruckten Mehrschichtleiterplatte.
DE59005035D1 (de) Leiterplatte für elektronische Steuergeräte und Verfahren zum Herstellen einer solchen Leiterplatte.
DE3689147D1 (de) Ein Verfahren zum Herstellen einer gedruckten Schaltungsplatte für Halbleiterschaltungen.
DE3769501D1 (de) Werkzeug und verfahren zum zusammenbau einer gedruckten leiterplatte.
JPS53109173A (en) Method of connecting pattern of multilayer printed circuit board
DE69431175D1 (de) Verfahren zur Herstellung einer Leiterplatte
DE69016752D1 (de) Verfahren zur Herstellung einer flexiblen gedruckten Schaltungsplatte.
KR890015480A (ko) 인쇄 배선판의 제조방법
AT377889B (de) Verfahren zum herstellen einer mit bauelementen bestueckten leiterplatte
DE69218035D1 (de) Verfahren zum Herstellen einer integrierten Schaltung

Legal Events

Date Code Title Description
8363 Opposition against the patent
8320 Willingness to grant licences declared (paragraph 23)
8331 Complete revocation