JPS5842262A - 混成集積回路のリ−ド線接続方法 - Google Patents

混成集積回路のリ−ド線接続方法

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Publication number
JPS5842262A
JPS5842262A JP56139656A JP13965681A JPS5842262A JP S5842262 A JPS5842262 A JP S5842262A JP 56139656 A JP56139656 A JP 56139656A JP 13965681 A JP13965681 A JP 13965681A JP S5842262 A JPS5842262 A JP S5842262A
Authority
JP
Japan
Prior art keywords
lead wires
lead wire
soldered
flat
metal pieces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56139656A
Other languages
English (en)
Other versions
JPS6347151B2 (ja
Inventor
Toshio Yamamoto
俊夫 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56139656A priority Critical patent/JPS5842262A/ja
Priority to US06/413,400 priority patent/US4542438A/en
Priority to GB08225156A priority patent/GB2106327B/en
Priority to DE19823233225 priority patent/DE3233225A1/de
Publication of JPS5842262A publication Critical patent/JPS5842262A/ja
Publication of JPS6347151B2 publication Critical patent/JPS6347151B2/ja
Granted legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • H05K3/4015Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01029Copper [Cu]
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01056Barium [Ba]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
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    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/1031Surface mounted metallic connector elements
    • H05K2201/10318Surface mounted metallic pins
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10962Component not directly connected to the PCB
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147Assembling terminal to base
    • Y10T29/49149Assembling terminal to base by metal fusion bonding

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明はセラ電ツタス基11’に厚膜導体によ)導体部
を形成した混成集積回路にリード線を接続する方法に関
する0 セラミックス基板に厚膜導体な錬成して導体−を形成し
た温威県積−mov−ド纏績l!方法は。
一般に第111に示すように、セラ2ツクス基板(鳳)
(以下基板と称す)および導体部(2)を貫通して小孔
(3)をあけ、一端部(4)にヘッディングなどにより
偏平部(5)を形成し九リード線(6)を小孔(3)に
下方からその他端部を挿入し、平坦面())を轟接させ
てはんだa呻によ)導体部(2)とリード線(6)とを
接合している。しかしこの方法はリード線中チップ部品
トラ7ジスタおよびICなどの半導体素子を基板(1)
上に設置し先後炉中を通して1回のりフローソルダリン
グで取付けできる利点を有する反面、リフロー後の各部
品のファンクシ璽ントリZングに際し、リード線(6)
、・・・が突出している丸めの取扱いに〈(、これらの
作業を自動化するのは極めて困難であり、また基板(1
)の多数の小孔(暮、・・・にそれ(れリード線(6)
、・・・を裏面から挿入す4の4作業性が悪く、自動化
%困難であるという不都合があった〇 これらの欠点を解決する方法として、リード線(6)以
外の各部品をリアローソルダリングで取付けた後7アン
タシ璽ントリ電ングし、その後先端部を前述のようにヘ
ッディングしたり一ド纏(6)を赤外線、レーザ光、は
んだごてなどによυ個々にはんだ付けする方法も考えら
れている。しかしこの方法も最初のりフローソルダーリ
ング後ファンクシ冒ントリ2ング前に洗浄し、さらにリ
ード線(6)・・・をはんだ付けした後に再び洗浄する
盛暑が生じ、ま九2回のはんだ付は部の加熱によって、
リード線(6)、・・・の接続部の導体(2)(λg−
Pd)に、はんだがくわれる現象が生じ、はんだ付は部
の強度劣化をもたらす不都合があり九。
また上述の方法とは別にバーカッシ冒ン#1接方法など
によシ直接リード線(6)、・・・を導体部(2)・・
・に溶接することも考えられているが、スプラッシ島の
発生が多く、ま九信頼性0LIIでも混成集積回路に適
用するには困難が多いという不都合#条る・本発明は、
上述の不都合を除去するためになされ丸もので、導体部
にそのリード線を接続すべき所定の位置に金属片を予め
はんだ付けした後、これとリード線とをシリーズS*す
ることKよル自動化を容易にするとともに信頼性をも向
上した混成集積回路のリード線接続方法である。
以下本発明の詳細を第2図およびls3図を参照しなが
らその一実施例によシ説明する。第2図において、基板
(1)上に厚膜ペースト印刷により導体部(2)を設け
て、従来と同様な処理によシ回路配線1ペースト部分に
IC中トランジスタなどの半導体素子およびコンデンサ
などの電気部品ae、・・・を載置するとともに、リー
ド線(6)、・・・を取付けるべき所定部位α力、・・
・例えば電極部にニッケル!丸はニッケルやすすをめっ
きした鋼片からなる金属片α・、・・・を載置して加熱
デを通しはんだ付けをした後洗浄する。このようにして
、リード線(6)、・・・が堆付けられていない状態で
はんだ付けの終了した各種電気部品ae、・・・に対し
、ファンクシ17トリZングヤ特性チエツクなどを行な
う。次に第3図に示すように、従来例と同様に一端部(
4)にヘッディングにより偏平部(5)が形成され九リ
ード線(0゜・・・の偏平部(5)の外側の平坦面(8
)、・・・を金属片側。
・・・に当接させ、溶接用の一方の電極としての圧電極
0!J、・・、他方の電極としての負電極(至)、・・
・を内側の平坦面(7)、・・・にそれぞれ蟲接して押
圧し、通電する。これにより電流は偏平部(5)、・・
・を通つて流れると同時に金属片側、・・・を介して矢
印c11)に示すように流れ、いわゆるシリーズ通電が
なされ。
金属片a・、・・・と外側の平坦面(8)、・・・とけ
複数個所において抵抗溶接される。なお本実施例におい
てはリード線(6)は鋼線であゐO また本発明方法により、シリーズ通電し丸鳩舎と、−極
をリード線(6)の他端部に設け、他極を金属片側に設
けてパーカツシwys*t、た場合とで引張強度、繰返
し曲げ@数などにつき比較した結果を第4図、第5図に
示すO第481は縦軸に引張シ強度をとヤ、横軸に資料
Hoをとり、0印は本発明のシリーズ溶接によるもので
あり、Δ印は/(−カッ9.:/111m1によるtの
で、リード線(6)性直徴0.5■で鋼線にすずめつき
を施し九40を使用し九〇本発明によるものが引張強*
 8kg付近なOK対し他方の%のが7kg付近であっ
て重置@O方が強直が大であることが明確に示されて−
る。また第S図は縦軸に45’繰返し曲げて折損するま
での回数をとったtので、横軸p印、−Δ印については
fa4図におけると同様であるO本図からt本発明によ
るものが5〜6回に集中しているのに対し、ノ(−カッ
シ嘗ン@*のものは1〜2回に集中していることが示さ
れているO 以上詳述したように1本発明の混成集積回路のリード線
接続方法は、金属片を所定部位にはんだ付けした後、シ
リーズ通電によりリード線先端部と金属片とを溶接する
ように構成したので、ファンクシ嘗ントリ2ングKII
Iしてはリード線はまだ職付けられていないので作業性
がよく、自動化も容易であり、またリード線の供給も従
来のように小孔を通す盛暑がないので自動化が容易であ
るOさらにまたシリーズ過電によp複数個所で@捺がな
されるので、極めて信頼性が向上するなどの効果を奏す
るもo”cあるOなお本実施例においてはリード線のヘ
ッディングはT字状に形成したが、これtC@定されf
、例えば5字状などに形成してもよく1畳は平jlIi
があればよい。
また溶接電源としては単相交流、三相交流、三相整流、
コンデンサ放電直流などいずれを用いてもよいことはい
うまでもない。
・4、図面の簡単な説明 第1図は従来のリード線接続方法をm羽する新面図、8
12図は本発明方法の一実施例を説明する断面図で、は
んだ付は工111I&明図、第3@は同じく溶接工mm
明図、第4図は本発明の一実施例によるリード線の接続
と従来の方法による接続とO引張〉強度比較図%第5図
は同じく繰返し曲げ強度比較図である。
(1)・・・セラきツクス基板、(2)・・・導体部。
(5)・・・偏平部、 (6)・・・リード線、 α力
・・・所定部位。
a・・・・金属片、 a−・・・°一方の電極。
(2)・・・他方の電極。
代理人 弁理士  則 近 憲 佑 (ほか1名) 第 1図 第2図      冨3図

Claims (1)

    【特許請求の範囲】
  1. セラ2ツクス基板に厚膜導体により形成され良導体部の
    所定部位に金属片をはんだ付けず石工1と、先端部に偏
    平部を形成したリード−〇上記量平部の外側の平坦面を
    上記金属片に轟嬢するニーと、一方の電極および他方の
    電極を上記偏平−にそれぞれ轟接して加圧し上記一方の
    電極から上記他方の電極へシリーズ通電させ上記偏平部
    および上記金属片を溶接する工1とを具備したことを畳
    黴とする混成集積回路013−ド纏接続方法0
JP56139656A 1981-09-07 1981-09-07 混成集積回路のリ−ド線接続方法 Granted JPS5842262A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56139656A JPS5842262A (ja) 1981-09-07 1981-09-07 混成集積回路のリ−ド線接続方法
US06/413,400 US4542438A (en) 1981-09-07 1982-08-31 Hybrid integrated circuit device
GB08225156A GB2106327B (en) 1981-09-07 1982-09-03 Lead connection to hybrid integrated circuit devices and method of applying the same
DE19823233225 DE3233225A1 (de) 1981-09-07 1982-09-07 Integrierte hybridschaltungsanordnung und verfahren zu ihrer herstellung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56139656A JPS5842262A (ja) 1981-09-07 1981-09-07 混成集積回路のリ−ド線接続方法

Publications (2)

Publication Number Publication Date
JPS5842262A true JPS5842262A (ja) 1983-03-11
JPS6347151B2 JPS6347151B2 (ja) 1988-09-20

Family

ID=15250342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56139656A Granted JPS5842262A (ja) 1981-09-07 1981-09-07 混成集積回路のリ−ド線接続方法

Country Status (4)

Country Link
US (1) US4542438A (ja)
JP (1) JPS5842262A (ja)
DE (1) DE3233225A1 (ja)
GB (1) GB2106327B (ja)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3412651A1 (de) * 1984-04-04 1985-10-17 Brown, Boveri & Cie Ag, 6800 Mannheim Verfahren zur herstellung eines leistungshalbleitermoduls
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US4542438A (en) 1985-09-17
JPS6347151B2 (ja) 1988-09-20
DE3233225C2 (ja) 1987-12-03
GB2106327B (en) 1985-03-13
GB2106327A (en) 1983-04-07
DE3233225A1 (de) 1983-03-24

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