DE69115852D1 - Verfahren zur Herstellung einer Leiterplatte - Google Patents

Verfahren zur Herstellung einer Leiterplatte

Info

Publication number
DE69115852D1
DE69115852D1 DE69115852T DE69115852T DE69115852D1 DE 69115852 D1 DE69115852 D1 DE 69115852D1 DE 69115852 T DE69115852 T DE 69115852T DE 69115852 T DE69115852 T DE 69115852T DE 69115852 D1 DE69115852 D1 DE 69115852D1
Authority
DE
Germany
Prior art keywords
production
circuit board
printed circuit
printed
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69115852T
Other languages
English (en)
Other versions
DE69115852T2 (de
Inventor
Seppo Pienimaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Mobile Phones Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Mobile Phones Ltd filed Critical Nokia Mobile Phones Ltd
Application granted granted Critical
Publication of DE69115852D1 publication Critical patent/DE69115852D1/de
Publication of DE69115852T2 publication Critical patent/DE69115852T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/092—Exposing inner circuit layers or metal planes at the walls of high aspect ratio holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
DE69115852T 1990-10-30 1991-10-02 Verfahren zur Herstellung einer Leiterplatte Expired - Fee Related DE69115852T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI905366A FI88241C (fi) 1990-10-30 1990-10-30 Foerfarande foer framstaellning av kretskort

Publications (2)

Publication Number Publication Date
DE69115852D1 true DE69115852D1 (de) 1996-02-08
DE69115852T2 DE69115852T2 (de) 1996-06-05

Family

ID=8531338

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69115852T Expired - Fee Related DE69115852T2 (de) 1990-10-30 1991-10-02 Verfahren zur Herstellung einer Leiterplatte

Country Status (5)

Country Link
US (1) US5665525A (de)
EP (1) EP0483979B1 (de)
JP (1) JPH04283992A (de)
DE (1) DE69115852T2 (de)
FI (1) FI88241C (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
FI105606B (fi) 1997-10-13 2000-09-15 Nokia Mobile Phones Ltd Optinen tiedonsiirtoyksikkö
US6174561B1 (en) 1998-01-30 2001-01-16 James M. Taylor Composition and method for priming substrate materials
US6555170B2 (en) 1998-01-30 2003-04-29 Duratech Industries, Inc. Pre-plate treating system
US6162365A (en) * 1998-03-04 2000-12-19 International Business Machines Corporation Pd etch mask for copper circuitization
US6078013A (en) * 1998-10-08 2000-06-20 International Business Machines Corporation Clover-leaf solder mask opening
KR100385976B1 (ko) * 1999-12-30 2003-06-02 삼성전자주식회사 회로기판 및 그 제조방법
JP3775970B2 (ja) * 2000-03-27 2006-05-17 新光電気工業株式会社 電子部品実装用基板の製造方法
JP3488888B2 (ja) * 2000-06-19 2004-01-19 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ用回路基板の製造方法及びそれを用いた半導体パッケージ用回路基板
KR100887894B1 (ko) * 2001-03-07 2009-03-11 소니 가부시끼 가이샤 프린트 배선판의 랜드부, 프린트 배선판의 제조 방법, 및프린트 배선판 실장 방법
US6753480B2 (en) * 2001-10-12 2004-06-22 Ultratera Corporation Printed circuit board having permanent solder mask
TW564530B (en) * 2002-07-03 2003-12-01 United Test Ct Inc Circuit board for flip-chip semiconductor package and fabrication method thereof
JP4023339B2 (ja) * 2003-03-05 2007-12-19 日立電線株式会社 配線板の製造方法
US20040198044A1 (en) * 2003-04-04 2004-10-07 Sheng-Chuan Huang Stacking photoresist image transferring method for fabricating a packaging substrate
US7264372B2 (en) * 2004-03-16 2007-09-04 Mag Instrument, Inc. Apparatus and method for aligning a substantial point source of light with a reflector feature
US20150013901A1 (en) * 2013-07-11 2015-01-15 Hsio Technologies, Llc Matrix defined electrical circuit structure
CN107920415B (zh) * 2016-10-06 2020-11-03 鹏鼎控股(深圳)股份有限公司 具厚铜线路的电路板及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3568312A (en) * 1968-10-04 1971-03-09 Hewlett Packard Co Method of making printed circuit boards
US3934335A (en) * 1974-10-16 1976-01-27 Texas Instruments Incorporated Multilayer printed circuit board
US4211603A (en) * 1978-05-01 1980-07-08 Tektronix, Inc. Multilayer circuit board construction and method
DE2932536A1 (de) * 1979-08-09 1981-02-26 Schering Ag Verfahren zur herstellung von gedruckten schaltungen
JPS5648198A (en) * 1979-09-26 1981-05-01 Matsushita Electric Ind Co Ltd Method of manufacturing flexible printed circuit board
DE3110528A1 (de) * 1981-03-18 1982-10-07 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur herstellung gedruckter schaltungen
GB8500906D0 (en) * 1985-01-15 1985-02-20 Prestwick Circuits Ltd Printed circuit boards
JPS61206293A (ja) * 1985-03-08 1986-09-12 日本ペイント株式会社 回路板の製造方法
US4915983A (en) * 1985-06-10 1990-04-10 The Foxboro Company Multilayer circuit board fabrication process
US4804615A (en) * 1985-08-08 1989-02-14 Macdermid, Incorporated Method for manufacture of printed circuit boards
US4737446A (en) * 1986-12-30 1988-04-12 E. I. Du Pont De Nemours And Company Method for making multilayer circuits using embedded catalyst receptors
US4927742A (en) * 1987-01-14 1990-05-22 Kollmorgen Corporation Multilayer printed wiring boards
US4931144A (en) * 1987-07-31 1990-06-05 Texas Instruments Incorporated Self-aligned nonnested sloped via

Also Published As

Publication number Publication date
DE69115852T2 (de) 1996-06-05
EP0483979A1 (de) 1992-05-06
FI905366A (fi) 1992-05-01
JPH04283992A (ja) 1992-10-08
FI88241B (fi) 1992-12-31
EP0483979B1 (de) 1995-12-27
US5665525A (en) 1997-09-09
FI88241C (fi) 1993-04-13
FI905366A0 (fi) 1990-10-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee