DE69408542D1 - Verfahren zur herstellung einer leiterplatte - Google Patents

Verfahren zur herstellung einer leiterplatte

Info

Publication number
DE69408542D1
DE69408542D1 DE69408542T DE69408542T DE69408542D1 DE 69408542 D1 DE69408542 D1 DE 69408542D1 DE 69408542 T DE69408542 T DE 69408542T DE 69408542 T DE69408542 T DE 69408542T DE 69408542 D1 DE69408542 D1 DE 69408542D1
Authority
DE
Germany
Prior art keywords
producing
circuit board
board
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69408542T
Other languages
English (en)
Other versions
DE69408542T2 (de
Inventor
John Frederick David Knopp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MacDermid Inc
Original Assignee
MacDermid Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MacDermid Inc filed Critical MacDermid Inc
Application granted granted Critical
Publication of DE69408542D1 publication Critical patent/DE69408542D1/de
Publication of DE69408542T2 publication Critical patent/DE69408542T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0565—Resist used only for applying catalyst, not for plating itself
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemically Coating (AREA)
DE69408542T 1993-12-03 1994-12-02 Verfahren zur herstellung einer leiterplatte Expired - Lifetime DE69408542T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9324848A GB2284509B (en) 1993-12-03 1993-12-03 Method of making a printed circuit board
PCT/GB1994/002651 WO1995015674A1 (en) 1993-12-03 1994-12-02 Method of making a printed circuit board

Publications (2)

Publication Number Publication Date
DE69408542D1 true DE69408542D1 (de) 1998-03-19
DE69408542T2 DE69408542T2 (de) 1998-10-01

Family

ID=10746102

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69408542T Expired - Lifetime DE69408542T2 (de) 1993-12-03 1994-12-02 Verfahren zur herstellung einer leiterplatte

Country Status (8)

Country Link
EP (1) EP0732040B1 (de)
JP (1) JPH09506468A (de)
AU (1) AU1320695A (de)
CA (1) CA2177708C (de)
DE (1) DE69408542T2 (de)
ES (1) ES2114303T3 (de)
GB (1) GB2284509B (de)
WO (1) WO1995015674A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5620612A (en) * 1995-08-22 1997-04-15 Macdermid, Incorporated Method for the manufacture of printed circuit boards
EP0762813A1 (de) * 1995-08-25 1997-03-12 Macdermid Incorporated Verfahren zur Herstellung von Leiterplatten
GB9520887D0 (en) * 1995-10-12 1995-12-13 Philips Electronics Nv Method of plating through holes of a printed circuit board
ES2125820B1 (es) * 1997-01-28 1999-11-16 Easy Hole International Ltd Procedimiento de fabricacion de placas de circuito impreso con conexion electrica entre caras.
EP0941021A1 (de) * 1998-03-06 1999-09-08 Easy Hole International, Ltd. Verfahren zur Herstellung gedruckter Leiterplatten mit elektrischer Verbindung zwischen den Seiten

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3269861A (en) * 1963-06-21 1966-08-30 Day Company Method for electroless copper plating
FR1431918A (fr) * 1965-02-05 1966-03-18 Jean Graniou Ets Procédé de nickelage et de finition de circuits imprimés
US4303798A (en) * 1979-04-27 1981-12-01 Kollmorgen Technologies Corporation Heat shock resistant printed circuit board assemblies
DE2920940A1 (de) * 1979-05-21 1980-12-04 Schering Ag Verfahren zur herstellung von gedruckten schaltungen
US4512829A (en) * 1983-04-07 1985-04-23 Satosen Co., Ltd. Process for producing printed circuit boards
JPH0834340B2 (ja) * 1988-12-09 1996-03-29 日立化成工業株式会社 配線板およびその製造法
JPH02174193A (ja) * 1988-12-26 1990-07-05 Nippon Mining Co Ltd プリント配線板の製造方法
GB9212395D0 (en) * 1992-06-11 1992-07-22 Knopp John F D Method of making a printed circuit board

Also Published As

Publication number Publication date
DE69408542T2 (de) 1998-10-01
JPH09506468A (ja) 1997-06-24
AU1320695A (en) 1995-06-19
GB2284509A (en) 1995-06-07
GB2284509B (en) 1997-11-26
EP0732040A1 (de) 1996-09-18
ES2114303T3 (es) 1998-05-16
GB9324848D0 (en) 1994-01-19
CA2177708C (en) 2004-02-17
CA2177708A1 (en) 1995-06-08
WO1995015674A1 (en) 1995-06-08
EP0732040B1 (de) 1998-02-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: KEHL & ETTMAYR, PATENTANWAELTE, 81679 MUENCHEN