DE3664022D1 - Packaged semiconductor chip - Google Patents

Packaged semiconductor chip

Info

Publication number
DE3664022D1
DE3664022D1 DE8686102790T DE3664022T DE3664022D1 DE 3664022 D1 DE3664022 D1 DE 3664022D1 DE 8686102790 T DE8686102790 T DE 8686102790T DE 3664022 T DE3664022 T DE 3664022T DE 3664022 D1 DE3664022 D1 DE 3664022D1
Authority
DE
Germany
Prior art keywords
semiconductor chip
packaged semiconductor
packaged
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8686102790T
Other languages
German (de)
English (en)
Inventor
Richard P Pashby
Douglas W Phelps
Sigvart J Samuelsen
William C Ward
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3664022D1 publication Critical patent/DE3664022D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/25—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/415—Leadframe inner leads serving as die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
DE8686102790T 1985-04-18 1986-03-04 Packaged semiconductor chip Expired DE3664022D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US72473685A 1985-04-18 1985-04-18

Publications (1)

Publication Number Publication Date
DE3664022D1 true DE3664022D1 (en) 1989-07-20

Family

ID=24911697

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686102790T Expired DE3664022D1 (en) 1985-04-18 1986-03-04 Packaged semiconductor chip

Country Status (5)

Country Link
EP (1) EP0198194B1 (enExample)
JP (1) JPS61241959A (enExample)
CA (1) CA1238119A (enExample)
DE (1) DE3664022D1 (enExample)
HK (1) HK56594A (enExample)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5296074A (en) * 1987-03-30 1994-03-22 E. I. Du Pont De Nemours And Company Method for bonding small electronic components
CA1290676C (en) * 1987-03-30 1991-10-15 William Frank Graham Method for bonding integrated circuit chips
US4796078A (en) * 1987-06-15 1989-01-03 International Business Machines Corporation Peripheral/area wire bonding technique
JPH0777226B2 (ja) * 1987-06-30 1995-08-16 株式会社日立製作所 半導体装置およびその製造方法
JP2644773B2 (ja) * 1987-10-28 1997-08-25 株式会社日立製作所 樹脂封止型半導体装置
JPH0724275B2 (ja) * 1987-11-06 1995-03-15 三菱電機株式会社 半導体装置
JP2706077B2 (ja) * 1988-02-12 1998-01-28 株式会社日立製作所 樹脂封止型半導体装置及びその製造方法
JP2708191B2 (ja) * 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
US5068712A (en) * 1988-09-20 1991-11-26 Hitachi, Ltd. Semiconductor device
US4937656A (en) * 1988-04-22 1990-06-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2647900B2 (ja) * 1988-05-12 1997-08-27 株式会社日立製作所 面実装超薄形半導体装置
JPH0215663A (ja) * 1988-07-04 1990-01-19 Tomoegawa Paper Co Ltd リードフレーム用両面接着テープ
JP2585738B2 (ja) * 1988-08-12 1997-02-26 株式会社日立製作所 半導体記憶装置
US4924291A (en) * 1988-10-24 1990-05-08 Motorola Inc. Flagless semiconductor package
JPH077816B2 (ja) * 1988-11-24 1995-01-30 株式会社東芝 半導体封止容器
JPH088329B2 (ja) * 1988-12-12 1996-01-29 三菱電機株式会社 半導体集積回路装置及びその製造方法
JP2809675B2 (ja) * 1989-03-20 1998-10-15 株式会社東芝 樹脂封止型半導体装置
US4916519A (en) * 1989-05-30 1990-04-10 International Business Machines Corporation Semiconductor package
EP0405330A3 (en) * 1989-06-29 1992-05-06 Motorola, Inc. Flagless leadframe, package and method
SG49886A1 (en) * 1989-06-30 1998-06-15 Texas Instruments Inc Balanced capacitance lead frame for integrated circuits
JPH088330B2 (ja) * 1989-07-19 1996-01-29 日本電気株式会社 Ｌｏｃ型リードフレームを備えた半導体集積回路装置
GB8918482D0 (en) * 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
JP2567961B2 (ja) * 1989-12-01 1996-12-25 株式会社日立製作所 半導体装置及びリ−ドフレ−ム
JPH0724270B2 (ja) * 1989-12-14 1995-03-15 株式会社東芝 半導体装置及びその製造方法
JP2801319B2 (ja) * 1989-12-28 1998-09-21 株式会社日立製作所 半導体装置
JP2528991B2 (ja) * 1990-02-28 1996-08-28 株式会社日立製作所 樹脂封止型半導体装置及びリ―ドフレ―ム
SG52794A1 (en) * 1990-04-26 1998-09-28 Hitachi Ltd Semiconductor device and method for manufacturing same
KR920020687A (ko) * 1991-04-16 1992-11-21 김광호 반도체 패키지
KR940006164B1 (ko) * 1991-05-11 1994-07-08 금성일렉트론 주식회사 반도체 패키지 및 그 제조방법
KR940003560B1 (ko) * 1991-05-11 1994-04-23 금성일렉트론 주식회사 적층형 반도체 패키지 및 그 제조방법.
JP2518569B2 (ja) * 1991-09-19 1996-07-24 三菱電機株式会社 半導体装置
JP2932785B2 (ja) * 1991-09-20 1999-08-09 富士通株式会社 半導体装置
KR940007757Y1 (ko) * 1991-11-14 1994-10-24 금성일렉트론 주식회사 반도체 패키지
US6372080B1 (en) 1993-03-29 2002-04-16 Hitachi Chemical Company, Ltd Process for fabricating a crack resistant resin encapsulated semiconductor chip package
US6046072A (en) * 1993-03-29 2000-04-04 Hitachi Chemical Company, Ltd. Process for fabricating a crack resistant resin encapsulated semiconductor chip package
US5994169A (en) * 1994-10-27 1999-11-30 Texas Instruments Incorporated Lead frame for integrated circuits and process of packaging
JP2715965B2 (ja) * 1995-03-13 1998-02-18 株式会社日立製作所 樹脂封止型半導体装置
JP2788885B2 (ja) * 1995-12-21 1998-08-20 山口日本電気株式会社 半導体装置用リードフレームおよび半導体装置
JP2806851B2 (ja) * 1995-12-27 1998-09-30 山口日本電気株式会社 半導体集積回路装置およびその製造方法
JP2911409B2 (ja) * 1996-07-22 1999-06-23 株式会社日立製作所 半導体装置
JPH11265971A (ja) 1998-03-17 1999-09-28 Hitachi Ltd Ｔｓｏｐ型半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421168A (en) * 1977-07-18 1979-02-17 Kyushu Nippon Electric Semiconductor
JPS5588356A (en) * 1978-12-27 1980-07-04 Hitachi Ltd Semiconductor device
US4331831A (en) * 1980-11-28 1982-05-25 Bell Telephone Laboratories, Incorporated Package for semiconductor integrated circuits
JPS6112095A (ja) * 1984-06-27 1986-01-20 日本電気株式会社 混成集積回路装置

Also Published As

Publication number Publication date
HK56594A (en) 1994-06-03
EP0198194A1 (en) 1986-10-22
EP0198194B1 (en) 1989-06-14
JPH0312781B2 (enExample) 1991-02-21
CA1238119A (en) 1988-06-14
JPS61241959A (ja) 1986-10-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition