DE3650401D1 - Programmierbare logische Schaltung mit konfigurierbarer Freigabe des Ausgangs. - Google Patents
Programmierbare logische Schaltung mit konfigurierbarer Freigabe des Ausgangs.Info
- Publication number
- DE3650401D1 DE3650401D1 DE3650401T DE3650401T DE3650401D1 DE 3650401 D1 DE3650401 D1 DE 3650401D1 DE 3650401 T DE3650401 T DE 3650401T DE 3650401 T DE3650401 T DE 3650401T DE 3650401 D1 DE3650401 D1 DE 3650401D1
- Authority
- DE
- Germany
- Prior art keywords
- registers
- programmable
- input
- output
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US80615885A | 1985-12-06 | 1985-12-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3650401D1 true DE3650401D1 (de) | 1995-10-26 |
DE3650401T2 DE3650401T2 (de) | 1996-05-15 |
Family
ID=25193456
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686309319T Expired - Lifetime DE3684573D1 (de) | 1985-12-06 | 1986-11-28 | Programmierbare logische vorrichtung. |
DE3650401T Expired - Fee Related DE3650401T2 (de) | 1985-12-06 | 1986-11-28 | Programmierbare logische Schaltung mit konfigurierbarer Freigabe des Ausgangs. |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686309319T Expired - Lifetime DE3684573D1 (de) | 1985-12-06 | 1986-11-28 | Programmierbare logische vorrichtung. |
Country Status (4)
Country | Link |
---|---|
EP (3) | EP0227329B1 (de) |
JP (3) | JP2562586B2 (de) |
AT (2) | ATE128291T1 (de) |
DE (2) | DE3684573D1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2548301B2 (ja) * | 1988-05-25 | 1996-10-30 | 富士通株式会社 | プログラマブル論理回路装置 |
US5479649A (en) * | 1992-05-01 | 1995-12-26 | Advanced Micro Devices, Inc. | Method and apparatus for forming a logical combination of signals from diagnostic nodes in an IC chip for passive observation at a dedicated diagnostic pin |
US5553070A (en) * | 1994-09-13 | 1996-09-03 | Riley; Robert E. | Data link module for time division multiplexing control systems |
US5986465A (en) * | 1996-04-09 | 1999-11-16 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a global shareable expander |
US6034540A (en) * | 1997-04-08 | 2000-03-07 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a lonely register |
US6107822A (en) | 1996-04-09 | 2000-08-22 | Altera Corporation | Logic element for a programmable logic integrated circuit |
JP4206203B2 (ja) * | 1999-03-04 | 2009-01-07 | アルテラ コーポレイション | プログラマブルロジック集積回路デバイスの相互接続ならびに入力/出力リソース |
US7076663B2 (en) * | 2001-11-06 | 2006-07-11 | International Business Machines Corporation | Integrated system security method |
CN104678284B (zh) * | 2013-12-03 | 2017-11-14 | 北京中电华大电子设计有限责任公司 | 一种提高芯片健壮性的新型测试控制电路和方法 |
CN117318734B (zh) * | 2023-11-27 | 2024-02-02 | 芯来智融半导体科技(上海)有限公司 | 芯片信号发射电路及方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5483341A (en) * | 1977-12-15 | 1979-07-03 | Nec Corp | Digital integrated circuit |
JPS56153839A (en) * | 1980-04-30 | 1981-11-28 | Nec Corp | Pla logical operation circuit |
JPS5945722A (ja) * | 1982-09-09 | 1984-03-14 | Matsushita Electric Ind Co Ltd | プログラマブルロジツクアレイ |
US4771285A (en) * | 1985-11-05 | 1988-09-13 | Advanced Micro Devices, Inc. | Programmable logic cell with flexible clocking and flexible feedback |
JPH0573294A (ja) * | 1991-09-17 | 1993-03-26 | Mitsubishi Electric Corp | マイクロプロセツサ |
-
1986
- 1986-11-28 EP EP86309319A patent/EP0227329B1/de not_active Expired - Lifetime
- 1986-11-28 AT AT91101263T patent/ATE128291T1/de active
- 1986-11-28 DE DE8686309319T patent/DE3684573D1/de not_active Expired - Lifetime
- 1986-11-28 EP EP91101263A patent/EP0428503B1/de not_active Expired - Lifetime
- 1986-11-28 EP EP19910101274 patent/EP0426655A3/de not_active Withdrawn
- 1986-11-28 AT AT86309319T patent/ATE74243T1/de not_active IP Right Cessation
- 1986-11-28 DE DE3650401T patent/DE3650401T2/de not_active Expired - Fee Related
- 1986-12-05 JP JP61291399A patent/JP2562586B2/ja not_active Expired - Lifetime
-
1996
- 1996-02-29 JP JP8042789A patent/JP2933206B2/ja not_active Expired - Lifetime
- 1996-02-29 JP JP8042790A patent/JP2933207B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0428503B1 (de) | 1995-09-20 |
EP0227329B1 (de) | 1992-03-25 |
JP2933206B2 (ja) | 1999-08-09 |
JPS62144416A (ja) | 1987-06-27 |
EP0426655A2 (de) | 1991-05-08 |
JPH08256053A (ja) | 1996-10-01 |
DE3684573D1 (de) | 1992-04-30 |
EP0428503A2 (de) | 1991-05-22 |
DE3650401T2 (de) | 1996-05-15 |
EP0227329A3 (en) | 1989-01-25 |
ATE74243T1 (de) | 1992-04-15 |
EP0428503A3 (en) | 1991-08-14 |
EP0227329A2 (de) | 1987-07-01 |
JP2933207B2 (ja) | 1999-08-09 |
JPH08256052A (ja) | 1996-10-01 |
EP0426655A3 (de) | 1991-07-03 |
ATE128291T1 (de) | 1995-10-15 |
JP2562586B2 (ja) | 1996-12-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: VANTIS CORP.)N.D.GES.D.STAATES DELAWARE), SUNNYVAL |
|
8339 | Ceased/non-payment of the annual fee |