DE69026200D1 - Programmierbares logisches Feld - Google Patents
Programmierbares logisches FeldInfo
- Publication number
- DE69026200D1 DE69026200D1 DE69026200T DE69026200T DE69026200D1 DE 69026200 D1 DE69026200 D1 DE 69026200D1 DE 69026200 T DE69026200 T DE 69026200T DE 69026200 T DE69026200 T DE 69026200T DE 69026200 D1 DE69026200 D1 DE 69026200D1
- Authority
- DE
- Germany
- Prior art keywords
- program
- signals
- iteration processing
- address
- switching devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Programmable Controllers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/434,797 US5021690A (en) | 1989-11-13 | 1989-11-13 | Programmable logic array apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69026200D1 true DE69026200D1 (de) | 1996-05-02 |
DE69026200T2 DE69026200T2 (de) | 1996-10-02 |
Family
ID=23725744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69026200T Expired - Fee Related DE69026200T2 (de) | 1989-11-13 | 1990-11-01 | Programmierbares logisches Feld |
Country Status (5)
Country | Link |
---|---|
US (1) | US5021690A (de) |
EP (1) | EP0428300B1 (de) |
JP (1) | JPH03187617A (de) |
AT (1) | ATE136177T1 (de) |
DE (1) | DE69026200T2 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5055716A (en) * | 1990-05-15 | 1991-10-08 | Siarc | Basic cell for bicmos gate array |
US5349691A (en) * | 1990-07-03 | 1994-09-20 | Xilinx, Inc. | Programming process for 3-level programming logic devices |
US5287018A (en) * | 1990-09-25 | 1994-02-15 | Dallas Semiconductor Corporation | Dynamic PLA time circuit |
US5274282A (en) * | 1990-10-02 | 1993-12-28 | Sgs-Thomson Microelectronics, S.R.L. | Monostabilized dynamic programmable logic array in CMOS technology |
US5367207A (en) * | 1990-12-04 | 1994-11-22 | Xilinx, Inc. | Structure and method for programming antifuses in an integrated circuit array |
US5189628A (en) * | 1991-03-11 | 1993-02-23 | National Semiconductor Corporation | System and method for partitioning PLA product terms into distinct logical groups |
JP3068382B2 (ja) * | 1993-09-29 | 2000-07-24 | 株式会社東芝 | プログラマブルロジックアレイ |
US6314549B1 (en) * | 1998-01-09 | 2001-11-06 | Jeng-Jye Shau | Power saving methods for programmable logic arrays |
US6609189B1 (en) * | 1998-03-12 | 2003-08-19 | Yale University | Cycle segmented prefix circuits |
DE10215771A1 (de) * | 2002-04-10 | 2003-11-20 | Infineon Technologies Ag | Konfigurierbares Rechenwerk |
US7167025B1 (en) | 2004-02-14 | 2007-01-23 | Herman Schmit | Non-sequentially configurable IC |
US7276933B1 (en) * | 2004-11-08 | 2007-10-02 | Tabula, Inc. | Reconfigurable IC that has sections running at different looperness |
US7330050B2 (en) | 2004-11-08 | 2008-02-12 | Tabula, Inc. | Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements |
US7317331B2 (en) * | 2004-11-08 | 2008-01-08 | Tabula, Inc. | Reconfigurable IC that has sections running at different reconfiguration rates |
US9203397B1 (en) | 2011-12-16 | 2015-12-01 | Altera Corporation | Delaying start of user design execution |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3215671C2 (de) * | 1982-04-27 | 1984-05-03 | Siemens AG, 1000 Berlin und 8000 München | Programmierbare Logikanordnung |
JPS61208316A (ja) * | 1985-03-12 | 1986-09-16 | Asahi Micro Syst Kk | プログラマブル論理回路 |
US4725748A (en) * | 1985-05-06 | 1988-02-16 | Tektronix, Inc. | High speed data acquisition utilizing multiple charge transfer delay lines |
IT1195119B (it) * | 1986-08-04 | 1988-10-12 | Cselt Centro Studi Lab Telecom | Perfezionamenti alle schiere logi che programmabili dinamiche a struttura nor nor realizzate in tecnolo gia c mos |
JPS6482819A (en) * | 1987-09-25 | 1989-03-28 | Toshiba Corp | Programmable logic array |
JP2547436B2 (ja) * | 1988-04-11 | 1996-10-23 | 富士通株式会社 | Pla制御方式 |
-
1989
- 1989-11-13 US US07/434,797 patent/US5021690A/en not_active Expired - Lifetime
-
1990
- 1990-11-01 EP EP90312002A patent/EP0428300B1/de not_active Expired - Lifetime
- 1990-11-01 AT AT90312002T patent/ATE136177T1/de not_active IP Right Cessation
- 1990-11-01 DE DE69026200T patent/DE69026200T2/de not_active Expired - Fee Related
- 1990-11-13 JP JP2308434A patent/JPH03187617A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
ATE136177T1 (de) | 1996-04-15 |
DE69026200T2 (de) | 1996-10-02 |
EP0428300A2 (de) | 1991-05-22 |
JPH03187617A (ja) | 1991-08-15 |
EP0428300A3 (en) | 1991-08-14 |
US5021690A (en) | 1991-06-04 |
EP0428300B1 (de) | 1996-03-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |