DE3687407D1 - Logische schaltung mit zusammengeschalteten mehrtorflip-flops. - Google Patents

Logische schaltung mit zusammengeschalteten mehrtorflip-flops.

Info

Publication number
DE3687407D1
DE3687407D1 DE8686114229T DE3687407T DE3687407D1 DE 3687407 D1 DE3687407 D1 DE 3687407D1 DE 8686114229 T DE8686114229 T DE 8686114229T DE 3687407 T DE3687407 T DE 3687407T DE 3687407 D1 DE3687407 D1 DE 3687407D1
Authority
DE
Germany
Prior art keywords
flip
flops
source
clock pulses
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686114229T
Other languages
English (en)
Other versions
DE3687407T2 (de
Inventor
Kazutoshi Shimizume
Takeshi Uematsu
Tetsu Haga
Youhei Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60229319A external-priority patent/JP2565189B2/ja
Priority claimed from JP61058931A external-priority patent/JPH07122652B2/ja
Priority claimed from JP61091828A external-priority patent/JP2536478B2/ja
Priority claimed from JP61091827A external-priority patent/JPH07122653B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE3687407D1 publication Critical patent/DE3687407D1/de
Publication of DE3687407T2 publication Critical patent/DE3687407T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356052—Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606—Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356069—Bistable circuits using additional transistors in the feedback circuit
    • H03K3/356078—Bistable circuits using additional transistors in the feedback circuit with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Color Television Image Signal Generators (AREA)
  • Optical Communication System (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Shift Register Type Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Electronic Switches (AREA)
DE8686114229T 1985-10-15 1986-10-14 Logische schaltung mit zusammengeschalteten mehrtorflip-flops. Expired - Fee Related DE3687407T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP60229319A JP2565189B2 (ja) 1985-10-15 1985-10-15 信号処理回路
JP61058931A JPH07122652B2 (ja) 1986-03-15 1986-03-15 フリップフロップ回路
JP61091828A JP2536478B2 (ja) 1986-04-21 1986-04-21 フリップフロップ回路
JP61091827A JPH07122653B2 (ja) 1986-04-21 1986-04-21 試験回路

Publications (2)

Publication Number Publication Date
DE3687407D1 true DE3687407D1 (de) 1993-02-11
DE3687407T2 DE3687407T2 (de) 1993-06-24

Family

ID=27463707

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686114229T Expired - Fee Related DE3687407T2 (de) 1985-10-15 1986-10-14 Logische schaltung mit zusammengeschalteten mehrtorflip-flops.

Country Status (6)

Country Link
US (1) US4733405A (de)
EP (1) EP0224004B1 (de)
KR (1) KR940009988B1 (de)
AT (1) ATE84165T1 (de)
AU (1) AU593028B2 (de)
DE (1) DE3687407T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0228156A3 (de) * 1985-11-07 1989-06-07 Control Data Corporation Prüfsystem für VLSI-Schaltungen
JPH0682146B2 (ja) * 1986-12-22 1994-10-19 日本電気株式会社 スキヤンパス方式の論理集積回路
JP2556017B2 (ja) * 1987-01-17 1996-11-20 日本電気株式会社 論理集積回路
US4879718A (en) * 1987-11-30 1989-11-07 Tandem Computers Incorporated Scan data path coupling
US5198999A (en) * 1988-09-12 1993-03-30 Kabushiki Kaisha Toshiba Serial input/output semiconductor memory including an output data latch circuit
JPH07111829B2 (ja) * 1988-09-12 1995-11-29 株式会社東芝 半導体メモリ
US4991175A (en) * 1989-10-06 1991-02-05 Hewlett-Packard Signature analysis
US5239206A (en) * 1990-03-06 1993-08-24 Advanced Micro Devices, Inc. Synchronous circuit with clock skew compensating function and circuits utilizing same
JP2945103B2 (ja) * 1990-05-15 1999-09-06 株式会社リコー テスト用スキャン回路装置
US5122685A (en) * 1991-03-06 1992-06-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5416367A (en) * 1991-03-06 1995-05-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
JPH04351118A (ja) * 1991-05-29 1992-12-04 Sharp Corp カウンタ回路
US5414714A (en) * 1992-03-26 1995-05-09 Motorola, Inc. Method and apparatus for scan testing an array in a data processing system
US5369752A (en) * 1992-06-01 1994-11-29 Motorola, Inc. Method and apparatus for shifting data in an array of storage elements in a data processing system
US5463338A (en) * 1993-06-07 1995-10-31 Vlsi Technology, Inc. Dual latch clocked LSSD and method
US5485466A (en) * 1993-10-04 1996-01-16 Motorola, Inc. Method and apparatus for performing dual scan path testing of an array in a data processing system
GB9405804D0 (en) * 1994-03-24 1994-05-11 Discovision Ass Scannable latch and method of using the same
US5544107A (en) * 1994-08-22 1996-08-06 Adaptec, Inc. Diagnostic data port for a LSI or VLSI integrated circuit
US5663669A (en) * 1994-12-14 1997-09-02 International Business Machines Corporation Circuitry and method for latching information
KR0158610B1 (en) * 1995-04-27 1998-12-15 Samsung Electronics Co Ltd Serial interface to memory using the interlaced scan
FR2739967B1 (fr) * 1995-10-16 1997-11-14 Sgs Thomson Microelectronics Procede d'initialisaiton d'un registre a decalage et registre associe
US5719516A (en) * 1995-12-20 1998-02-17 Advanced Micro Devices, Inc. Lock generator circuit for use with a dual edge register that provides a separate enable for each use of an input clock signal
US5754070A (en) * 1996-11-19 1998-05-19 Vlsi Technology, Inc. Metastableproof flip-flop
JPH11328947A (ja) * 1998-05-18 1999-11-30 Nec Corp 大規模ｆｉｆｏ回路
EP1515345A1 (de) * 1999-02-02 2005-03-16 Fujitsu Limited Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung
US6614263B2 (en) * 2002-02-05 2003-09-02 Logicvision, Inc. Method and circuitry for controlling clocks of embedded blocks during logic bist test mode
US7262648B2 (en) * 2004-08-03 2007-08-28 Marvell International Ltd. Two-latch clocked-LSSD flip-flop
US20060085707A1 (en) * 2004-09-28 2006-04-20 Texas Instruments Incorporated High speed energy conserving scan architecture
FR3115149B1 (fr) 2020-10-09 2024-02-23 St Microelectronics Grenoble 2 Dispositif de mémorisation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291386A (en) * 1978-11-30 1981-09-22 Sperry Corporation Pseudorandom number generator
JPS57116424A (en) * 1981-01-13 1982-07-20 Toshiba Corp Parallel-to-serial converting circuit
US4408298A (en) * 1981-06-26 1983-10-04 Rca Corporation Pseudo random number generator apparatus
DE3274910D1 (en) * 1982-09-28 1987-02-05 Ibm Device for loading and reading different chains of bistable circuits in a data processing system
US4534030A (en) * 1982-12-20 1985-08-06 International Business Machines Corporation Self-clocked signature analyzer
JPS59151537A (ja) * 1983-01-29 1984-08-30 Toshiba Corp 相補ｍｏｓ形回路
US4534028A (en) * 1983-12-01 1985-08-06 Siemens Corporate Research & Support, Inc. Random testing using scan path technique
US4601033A (en) * 1984-01-16 1986-07-15 Siemens Corporate Research & Suppport, Inc. Circuit testing apparatus employing signature analysis
US4611183A (en) * 1984-04-30 1986-09-09 Motorola, Inc. Digital decorrelating random data generator
US4590601A (en) * 1984-12-24 1986-05-20 Gte Communication Systems Corporation Pseudo random framing detector circuit

Also Published As

Publication number Publication date
US4733405A (en) 1988-03-22
DE3687407T2 (de) 1993-06-24
EP0224004B1 (de) 1992-12-30
KR870004384A (ko) 1987-05-09
KR940009988B1 (ko) 1994-10-19
ATE84165T1 (de) 1993-01-15
AU6392686A (en) 1987-04-16
AU593028B2 (en) 1990-02-01
EP0224004A3 (en) 1990-08-16
EP0224004A2 (de) 1987-06-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: PATENTANWAELTE MUELLER & HOFFMANN, 81667 MUENCHEN

8339 Ceased/non-payment of the annual fee