FR3115149B1 - Dispositif de mémorisation - Google Patents

Dispositif de mémorisation Download PDF

Info

Publication number
FR3115149B1
FR3115149B1 FR2010332A FR2010332A FR3115149B1 FR 3115149 B1 FR3115149 B1 FR 3115149B1 FR 2010332 A FR2010332 A FR 2010332A FR 2010332 A FR2010332 A FR 2010332A FR 3115149 B1 FR3115149 B1 FR 3115149B1
Authority
FR
France
Prior art keywords
signal
dispt1
select1
disp1
receive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2010332A
Other languages
English (en)
Other versions
FR3115149A1 (fr
Inventor
Haddad Elias El
Tanguy Tromelin
Patrick Bougant
Christophe Matheron
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Priority to FR2010332A priority Critical patent/FR3115149B1/fr
Priority to US16/951,645 priority patent/US11211932B1/en
Priority to US17/556,365 priority patent/US11901894B2/en
Publication of FR3115149A1 publication Critical patent/FR3115149A1/fr
Application granted granted Critical
Publication of FR3115149B1 publication Critical patent/FR3115149B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/007—Register arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Logic Circuits (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • User Interface Of Digital Computer (AREA)

Abstract

Dispositif de mémorisation (DISP1) d’une donnée, le dispositif de mémorisation (DISP1) comprenant une porte logique (G1) de type ET comprenant une première entrée (11A), configurée pour être reliée à un dispositif tiers (DISPT1) et pour en recevoir un signal de sélection (SELECT1), une deuxième entrée (11B), configurée pour être reliée au dispositif tiers (DISPT1) et pour en recevoir un signal d’état (ETAT1) et une sortie (21), configurée pour émettre un signal de sortie lorsque le signal de sélection (SELECT1) et le signal d’état (ETAT1) sont reçus. Figure pour l’abrégé : Figure 2
FR2010332A 2020-10-09 2020-10-09 Dispositif de mémorisation Active FR3115149B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2010332A FR3115149B1 (fr) 2020-10-09 2020-10-09 Dispositif de mémorisation
US16/951,645 US11211932B1 (en) 2020-10-09 2020-11-18 Storage device
US17/556,365 US11901894B2 (en) 2020-10-09 2021-12-20 Method of operating a storage device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2010332 2020-10-08
FR2010332A FR3115149B1 (fr) 2020-10-09 2020-10-09 Dispositif de mémorisation

Publications (2)

Publication Number Publication Date
FR3115149A1 FR3115149A1 (fr) 2022-04-15
FR3115149B1 true FR3115149B1 (fr) 2024-02-23

Family

ID=74668923

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2010332A Active FR3115149B1 (fr) 2020-10-09 2020-10-09 Dispositif de mémorisation

Country Status (2)

Country Link
US (2) US11211932B1 (fr)
FR (1) FR3115149B1 (fr)

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE84165T1 (de) * 1985-10-15 1993-01-15 Sony Corp Logische schaltung mit zusammengeschalteten mehrtorflip-flops.
US5680318A (en) 1990-12-21 1997-10-21 Synopsys Inc. Synthesizer for generating a logic network using a hardware independent description
DE69614821T2 (de) 1996-01-19 2002-01-17 St Microelectronics Srl Geschalteter Taktgeber
TW478255B (en) * 2000-12-13 2002-03-01 Via Tech Inc Circuit static timing analysis method using generated clock
US6586966B1 (en) * 2001-09-13 2003-07-01 Altera Corporation Data latch with low-power bypass mode
US7073086B2 (en) * 2001-11-27 2006-07-04 Sun Microsystems, Inc. System for controlling a tunable delay by transferring a signal from a first plurality of points along a first propagating circuit to a second plurality of points along a second propagating circuit
US6777977B1 (en) * 2002-05-01 2004-08-17 Actel Corporation Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
US7242235B1 (en) * 2005-02-25 2007-07-10 Exar Corporation Dual data rate flip-flop
EP2823081A1 (fr) * 2012-03-05 2015-01-14 First Solar, Inc Procédé et appareil destinés à former un oxyde conducteur transparent à l'aide d'hydrogène
US8773896B2 (en) * 2012-05-18 2014-07-08 Alexander Mikhailovich Shukh Nonvolatile latch circuit
US9658971B2 (en) * 2013-09-11 2017-05-23 Nxp Usa, Inc. Universal SPI (serial peripheral interface)
US9385724B1 (en) * 2013-10-03 2016-07-05 Altera Corporation Methods for operating configurable storage and processing blocks at double and single data rates
US10141916B2 (en) * 2015-09-01 2018-11-27 Samsung Electronics Co., Ltd. High-speed flip-flop semiconductor device
EP3503404B1 (fr) * 2017-12-22 2021-10-27 NXP USA, Inc. Par circuit et procédé diviseur de fréquence numérique à nombre entier impair

Also Published As

Publication number Publication date
US11211932B1 (en) 2021-12-28
US11901894B2 (en) 2024-02-13
US20220116043A1 (en) 2022-04-14
FR3115149A1 (fr) 2022-04-15

Similar Documents

Publication Publication Date Title
US7483520B2 (en) Method and apparatus for prompting a cellular telephone user with instructions
US10582033B2 (en) Method of providing information and mobile telecommunication terminal thereof
US8644805B2 (en) Smart-phone answering service for handling incoming calls
WO2018040040A1 (fr) Dispositif et procédé de communication de message
US11829318B2 (en) Handshake protocol circuit, chip and computer device
US3936805A (en) Dictation system for storing and retrieving audio information
US20110077047A1 (en) Method and apparatus for managing multimedia communication recordings
FR3115149B1 (fr) Dispositif de mémorisation
CN111507698A (zh) 用于转账的处理方法和装置、计算设备及介质
CN110046052B (zh) 一种服务调用方法及装置
US20150089420A1 (en) Information processing apparatus, and information processing method
CN108304313A (zh) 一种用于数据测试的装置、客户端及方法
US20140192966A1 (en) Recording method, recording device, and electronic device
US11158319B2 (en) Information processing system, method, device and equipment
WO2019128531A1 (fr) Procédé, appareil et dispositif d'affichage d'enveloppe rouge
US6452937B1 (en) Card-based voice messaging system
KR20040007757A (ko) 텍스트 투 스피치(티티에스) 시스템에 이용하기 위한향상된 스피치 데이터를 포함시키는 텍스트 데이터 부호화방법, 복호화 방법, 티티에스 시스템 및 이를 포함하는이동 전화
US20050136954A1 (en) Entering information using terminals with limited I/O capabilities
TW202032394A (zh) 資料處理方法、裝置及設備
KR102350943B1 (ko) 집적 회로에 대한 소비 전력을 예측하는 방법 및 이를 수행하는 소비 전력 예측 시스템
US20170280309A1 (en) Method and terminal for calling application
US10657060B1 (en) Prefetching partial bitstreams
WO2020119299A1 (fr) Procédé et dispositif de fusion de modèle
CN107025201B (zh) 用于设备匹配的方法及用户设备
CN105321565A (zh) 有源驱动器和具有该有源驱动器的半导体器件

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20220415

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4