DE3617141A1 - Halbleiterbaueinheit mit integrierter schaltung und schmelzsicherungsstrecke - Google Patents

Halbleiterbaueinheit mit integrierter schaltung und schmelzsicherungsstrecke

Info

Publication number
DE3617141A1
DE3617141A1 DE19863617141 DE3617141A DE3617141A1 DE 3617141 A1 DE3617141 A1 DE 3617141A1 DE 19863617141 DE19863617141 DE 19863617141 DE 3617141 A DE3617141 A DE 3617141A DE 3617141 A1 DE3617141 A1 DE 3617141A1
Authority
DE
Germany
Prior art keywords
fuse link
fuse
insulating layer
film
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19863617141
Other languages
German (de)
English (en)
Other versions
DE3617141C2 (enrdf_load_stackoverflow
Inventor
Hiroshi Itami Hyogo Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3617141A1 publication Critical patent/DE3617141A1/de
Application granted granted Critical
Publication of DE3617141C2 publication Critical patent/DE3617141C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE19863617141 1985-05-23 1986-05-22 Halbleiterbaueinheit mit integrierter schaltung und schmelzsicherungsstrecke Granted DE3617141A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60110943A JPH0719842B2 (ja) 1985-05-23 1985-05-23 半導体装置の冗長回路

Publications (2)

Publication Number Publication Date
DE3617141A1 true DE3617141A1 (de) 1986-11-27
DE3617141C2 DE3617141C2 (enrdf_load_stackoverflow) 1993-08-05

Family

ID=14548486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863617141 Granted DE3617141A1 (de) 1985-05-23 1986-05-22 Halbleiterbaueinheit mit integrierter schaltung und schmelzsicherungsstrecke

Country Status (4)

Country Link
US (1) US4774561A (enrdf_load_stackoverflow)
JP (1) JPH0719842B2 (enrdf_load_stackoverflow)
KR (1) KR920000227B1 (enrdf_load_stackoverflow)
DE (1) DE3617141A1 (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3731621A1 (de) * 1987-09-19 1989-03-30 Texas Instruments Deutschland Verfahren zum herstellen einer elektrisch programmierbaren integrierten schaltung
EP0618620A1 (en) * 1993-04-01 1994-10-05 Advanced Micro Devices, Inc. Semiconductor fuse structures
DE19707312A1 (de) * 1997-02-11 1998-08-20 Thesys Ges Fuer Mikroelektroni Schaltungsanordnung zur Verbesserung der Zuverlässigkeit beim Prüfen integrierter Schaltkreise

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63140550A (ja) * 1986-12-01 1988-06-13 Mitsubishi Electric Corp 冗長回路用電気ヒユ−ズ
US5025300A (en) * 1989-06-30 1991-06-18 At&T Bell Laboratories Integrated circuits having improved fusible links
JPH04212426A (ja) * 1990-06-21 1992-08-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5335361A (en) * 1991-12-11 1994-08-02 Motorola, Inc. Integrated circuit module with devices interconnected by electromagnetic waves
JP2797929B2 (ja) * 1993-10-22 1998-09-17 日本電気株式会社 半導体装置
US5444287A (en) * 1994-08-10 1995-08-22 International Business Machines Corporation Thermally activated noise immune fuse
US5650355A (en) * 1995-03-30 1997-07-22 Texas Instruments Incorporated Process of making and process of trimming a fuse in a top level metal and in a step
US5521116A (en) * 1995-04-24 1996-05-28 Texas Instruments Incorporated Sidewall formation process for a top lead fuse
US5760674A (en) * 1995-11-28 1998-06-02 International Business Machines Corporation Fusible links with improved interconnect structure
US5886320A (en) * 1996-09-03 1999-03-23 International Business Machines Corporation Laser ablation with transmission matching for promoting energy coupling to a film stack
JP3081994B2 (ja) * 1997-10-22 2000-08-28 セイコーインスツルメンツ株式会社 半導体装置
US6259146B1 (en) 1998-07-17 2001-07-10 Lsi Logic Corporation Self-aligned fuse structure and method with heat sink
US6413848B1 (en) * 1998-07-17 2002-07-02 Lsi Logic Corporation Self-aligned fuse structure and method with dual-thickness dielectric
US6633055B2 (en) 1999-04-30 2003-10-14 International Business Machines Corporation Electronic fuse structure and method of manufacturing
JP3650281B2 (ja) * 1999-05-07 2005-05-18 セイコーインスツル株式会社 半導体装置
US6210995B1 (en) 1999-09-09 2001-04-03 International Business Machines Corporation Method for manufacturing fusible links in a semiconductor device
US7651893B2 (en) * 2005-12-27 2010-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Metal electrical fuse structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075926A2 (en) * 1981-09-30 1983-04-06 Hitachi, Ltd. Semiconductor integrated circuit device
EP0078165A2 (en) * 1981-10-28 1983-05-04 Kabushiki Kaisha Toshiba A semiconductor device having a control wiring layer
EP0083211A2 (en) * 1981-12-28 1983-07-06 Fujitsu Limited Semiconductor device with fuse
DE3428565A1 (de) * 1983-08-18 1985-03-07 General Electric Co., Schenectady, N.Y. Antireflexionsueberzug fuer optische lithographie

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584819B2 (ja) * 1975-08-28 1983-01-27 株式会社東芝 ハンドウタイソウチ
JPS6059678B2 (ja) * 1981-10-28 1985-12-26 株式会社東芝 プログラマブル・リ−ド・オンリ・メモリ素子
JPS60132344A (ja) * 1983-12-20 1985-07-15 Nec Corp 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075926A2 (en) * 1981-09-30 1983-04-06 Hitachi, Ltd. Semiconductor integrated circuit device
EP0078165A2 (en) * 1981-10-28 1983-05-04 Kabushiki Kaisha Toshiba A semiconductor device having a control wiring layer
EP0083211A2 (en) * 1981-12-28 1983-07-06 Fujitsu Limited Semiconductor device with fuse
DE3428565A1 (de) * 1983-08-18 1985-03-07 General Electric Co., Schenectady, N.Y. Antireflexionsueberzug fuer optische lithographie

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Smith, R.T. et.al.: Laser Programmable Redundancy and Field Improvement in a 64K DRAM. In: IEEE Journal of Solid-State Circuits, Bd. SC-16, Nr. 5, Okt. 1981, S. 506-513 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3731621A1 (de) * 1987-09-19 1989-03-30 Texas Instruments Deutschland Verfahren zum herstellen einer elektrisch programmierbaren integrierten schaltung
US4882293A (en) * 1987-09-19 1989-11-21 Texas Instruments Deutschland Gmbh Method of making an electrically programmable integrated circuit containing meltable contact bridges
EP0618620A1 (en) * 1993-04-01 1994-10-05 Advanced Micro Devices, Inc. Semiconductor fuse structures
DE19707312A1 (de) * 1997-02-11 1998-08-20 Thesys Ges Fuer Mikroelektroni Schaltungsanordnung zur Verbesserung der Zuverlässigkeit beim Prüfen integrierter Schaltkreise
DE19707312C2 (de) * 1997-02-11 2002-10-24 X Fab Semiconductor Foundries Schaltungsanordnung zur Verbesserung der Zuverlässigkeit beim Prüfen integrierter Schaltkreise

Also Published As

Publication number Publication date
DE3617141C2 (enrdf_load_stackoverflow) 1993-08-05
KR920000227B1 (ko) 1992-01-10
JPS61268042A (ja) 1986-11-27
US4774561A (en) 1988-09-27
KR860009487A (ko) 1986-12-23
JPH0719842B2 (ja) 1995-03-06

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee