DE3587223T2 - Unabhängige Matrixtaktierung. - Google Patents

Unabhängige Matrixtaktierung.

Info

Publication number
DE3587223T2
DE3587223T2 DE85105715T DE3587223T DE3587223T2 DE 3587223 T2 DE3587223 T2 DE 3587223T2 DE 85105715 T DE85105715 T DE 85105715T DE 3587223 T DE3587223 T DE 3587223T DE 3587223 T2 DE3587223 T2 DE 3587223T2
Authority
DE
Germany
Prior art keywords
independent matrix
matrix timing
timing
independent
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE85105715T
Other languages
English (en)
Other versions
DE3587223D1 (de
Inventor
Walter S Klara
Theodore W Kwap
Victor Marcello
Robert A Rasmussen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3587223D1 publication Critical patent/DE3587223D1/de
Publication of DE3587223T2 publication Critical patent/DE3587223T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
DE85105715T 1984-05-18 1985-05-10 Unabhängige Matrixtaktierung. Expired - Fee Related DE3587223T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/611,817 US4608669A (en) 1984-05-18 1984-05-18 Self contained array timing

Publications (2)

Publication Number Publication Date
DE3587223D1 DE3587223D1 (de) 1993-05-06
DE3587223T2 true DE3587223T2 (de) 1993-10-07

Family

ID=24450522

Family Applications (1)

Application Number Title Priority Date Filing Date
DE85105715T Expired - Fee Related DE3587223T2 (de) 1984-05-18 1985-05-10 Unabhängige Matrixtaktierung.

Country Status (4)

Country Link
US (1) US4608669A (de)
EP (1) EP0161639B1 (de)
JP (1) JPS60245275A (de)
DE (1) DE3587223T2 (de)

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US4763303A (en) * 1986-02-24 1988-08-09 Motorola, Inc. Write-drive data controller
US4825416A (en) * 1986-05-07 1989-04-25 Advanced Micro Devices, Inc. Integrated electronic memory circuit with internal timing and operable in both latch-based and register-based systems
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US4789960A (en) * 1987-01-30 1988-12-06 Rca Licensing Corporation Dual port video memory system having semi-synchronous data input and data output
JPH0612632B2 (ja) * 1987-02-27 1994-02-16 日本電気株式会社 メモリ回路
JP2684365B2 (ja) * 1987-04-24 1997-12-03 株式会社日立製作所 半導体記憶装置
JP2659095B2 (ja) * 1987-06-30 1997-09-30 富士通株式会社 ゲートアレイ及びメモリを有する半導体集積回路装置
US5587962A (en) * 1987-12-23 1996-12-24 Texas Instruments Incorporated Memory circuit accommodating both serial and random access including an alternate address buffer register
US5093807A (en) 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US4878209A (en) * 1988-03-17 1989-10-31 International Business Machines Corporation Macro performance test
US5142637A (en) * 1988-11-29 1992-08-25 Solbourne Computer, Inc. Dynamic video RAM incorporating single clock random port control
USRE35680E (en) * 1988-11-29 1997-12-02 Matsushita Electric Industrial Co., Ltd. Dynamic video RAM incorporating on chip vector/image mode line modification
US5077690A (en) * 1989-08-09 1991-12-31 Atmel Corporation Memory input data test arrangement
US5235566A (en) * 1989-09-07 1993-08-10 Amdahl Corporation Clock skew measurement technique
JP2936616B2 (ja) * 1990-02-01 1999-08-23 日本電気株式会社 テスト回路
JP2519580B2 (ja) * 1990-06-19 1996-07-31 三菱電機株式会社 半導体集積回路
JP3007475B2 (ja) * 1992-06-05 2000-02-07 三菱電機株式会社 メモリ装置
US5309037A (en) * 1992-07-08 1994-05-03 International Business Machines Corporation Power-on reset circuit with arbitrary output prevention
JPH0677827A (ja) * 1992-07-17 1994-03-18 Asama Erekurafuto Kk Ａ／ｄ変換器評価装置
JPH0643220A (ja) * 1992-07-23 1994-02-18 Hitachi Ltd 半導体集積回路装置
US5442640A (en) * 1993-01-19 1995-08-15 International Business Machines Corporation Test and diagnosis of associated output logic for products having embedded arrays
US5572717A (en) * 1994-04-06 1996-11-05 Altera Corporation Method and apparatus for assigning and analyzing timing specifications in a computer aided engineering program
JP3180883B2 (ja) * 1995-04-24 2001-06-25 日本電気株式会社 半導体記憶装置
US5692165A (en) * 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
US5663965A (en) * 1995-10-06 1997-09-02 International Business Machines Corp. Apparatus and method for testing a memory array
US5995570A (en) * 1997-06-27 1999-11-30 International Business Machines Corporation Recovering a clock signal in a multimedia network using time stamps
US5907508A (en) * 1997-10-28 1999-05-25 International Business Machines Corporation Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell
US5877976A (en) * 1997-10-28 1999-03-02 International Business Machines Corporation Memory system having a vertical bitline topology and method therefor
US5870349A (en) * 1997-10-28 1999-02-09 International Business Machines Corporation Data processing system and method for generating memory control signals with clock skew tolerance
US5956286A (en) * 1997-10-28 1999-09-21 International Business Machines Corporation Data processing system and method for implementing a multi-port memory cell
US6061285A (en) * 1999-11-10 2000-05-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of executing earlier command operation in test mode
US6760261B2 (en) * 2002-09-25 2004-07-06 Infineon Technologies Ag DQS postamble noise suppression by forcing a minimum pulse length
JP4957719B2 (ja) * 2006-02-28 2012-06-20 富士通株式会社 Ｒａｍマクロ、そのタイミング生成回路
JP2008097699A (ja) * 2006-10-11 2008-04-24 Nec Electronics Corp 半導体記憶装置

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US3420991A (en) * 1965-04-29 1969-01-07 Rca Corp Error detection system
US3474421A (en) * 1965-06-16 1969-10-21 Burroughs Corp Memory core testing apparatus
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US3633174A (en) * 1970-04-14 1972-01-04 Us Navy Memory system having self-adjusting strobe timing
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US3921142A (en) * 1973-09-24 1975-11-18 Texas Instruments Inc Electronic calculator chip having test input and output
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US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961251A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US3944800A (en) * 1975-08-04 1976-03-16 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement
IT1047437B (it) * 1975-10-08 1980-09-10 Cselt Centro Studi Lab Telecom Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo
US4001818A (en) * 1975-10-22 1977-01-04 Storage Technology Corporation Digital circuit failure detector
US4055754A (en) * 1975-12-22 1977-10-25 Chesley Gilman D Memory device and method of testing the same
US4066880A (en) * 1976-03-30 1978-01-03 Engineered Systems, Inc. System for pretesting electronic memory locations and automatically identifying faulty memory sections
JPS53117342A (en) * 1977-03-23 1978-10-13 Nec Corp Memory unit
JPS5435052A (en) * 1977-08-19 1979-03-14 Yasunori Nara Conveying device for fine piece by strong wind
US4171765A (en) * 1977-08-29 1979-10-23 Data General Corporation Error detection system
DE2829709C2 (de) * 1978-07-06 1984-02-23 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Anordnung zur Erzeugung zeitlich unmittelbar aufeinanderfolgender Impulszyklen
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
JPS5538603A (en) * 1978-09-04 1980-03-18 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device
DE2842750A1 (de) * 1978-09-30 1980-04-10 Ibm Deutschland Verfahren und anordnung zur pruefung von durch monolithisch integrierten halbleiterschaltungen dargestellten sequentiellen schaltungen
US4195770A (en) * 1978-10-24 1980-04-01 Burroughs Corporation Test generator for random access memories
US4227244A (en) * 1978-11-30 1980-10-07 Sperry Corporation Closed loop address
US4290137A (en) * 1979-12-26 1981-09-15 Honeywell Information Systems Inc. Apparatus and method of testing CML circuits
US4363124A (en) * 1980-06-26 1982-12-07 International Business Machines Corp. Recirculating loop memory array tester
JPS5755598A (en) * 1980-09-18 1982-04-02 Nec Corp Memory integrated circuit
US4404519A (en) * 1980-12-10 1983-09-13 International Business Machine Company Testing embedded arrays in large scale integrated circuits
US4481627A (en) * 1981-10-30 1984-11-06 Honeywell Information Systems Inc. Embedded memory testing method and apparatus
JPS58159293A (ja) * 1982-03-17 1983-09-21 Fujitsu Ltd メモリ素子制御方式
US4507761A (en) * 1982-04-20 1985-03-26 Mostek Corporation Functional command for semiconductor memory
JPS58201149A (ja) * 1982-05-20 1983-11-22 Toshiba Corp 集積回路

Also Published As

Publication number Publication date
JPS60245275A (ja) 1985-12-05
US4608669A (en) 1986-08-26
EP0161639A3 (en) 1988-10-05
DE3587223D1 (de) 1993-05-06
EP0161639A2 (de) 1985-11-21
JPH0411960B2 (de) 1992-03-03
EP0161639B1 (de) 1993-03-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee