IT1047437B - Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo - Google Patents

Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo

Info

Publication number
IT1047437B
IT1047437B IT69494/75A IT6949475A IT1047437B IT 1047437 B IT1047437 B IT 1047437B IT 69494/75 A IT69494/75 A IT 69494/75A IT 6949475 A IT6949475 A IT 6949475A IT 1047437 B IT1047437 B IT 1047437B
Authority
IT
Italy
Prior art keywords
cycle
inverter
words
memory
inverters
Prior art date
Application number
IT69494/75A
Other languages
English (en)
Inventor
Ween D Van
Martinus Wouter
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to IT69494/75A priority Critical patent/IT1047437B/it
Priority to NLAANVRAGE7610819,A priority patent/NL179097C/xx
Priority to DE2644733A priority patent/DE2644733C3/de
Priority to US05/730,723 priority patent/US4049956A/en
Application granted granted Critical
Publication of IT1047437B publication Critical patent/IT1047437B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
IT69494/75A 1975-10-08 1975-10-08 Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo IT1047437B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT69494/75A IT1047437B (it) 1975-10-08 1975-10-08 Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo
NLAANVRAGE7610819,A NL179097C (nl) 1975-10-08 1976-09-30 Werkwijze en inrichting voor het toetsen van de juiste werking van een geheugen.
DE2644733A DE2644733C3 (de) 1975-10-08 1976-10-04 Verfahren und Vorrichtung zum direkten Überprüfen des fehlerfreien Betriebs von Speichern bei der sequentiellen Datenverarbeitung
US05/730,723 US4049956A (en) 1975-10-08 1976-10-08 Method of and means for in-line testing of a memory operating in time-division mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT69494/75A IT1047437B (it) 1975-10-08 1975-10-08 Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo

Publications (1)

Publication Number Publication Date
IT1047437B true IT1047437B (it) 1980-09-10

Family

ID=11312257

Family Applications (1)

Application Number Title Priority Date Filing Date
IT69494/75A IT1047437B (it) 1975-10-08 1975-10-08 Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo

Country Status (4)

Country Link
US (1) US4049956A (it)
DE (1) DE2644733C3 (it)
IT (1) IT1047437B (it)
NL (1) NL179097C (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4360917A (en) * 1979-02-07 1982-11-23 The Warner & Swasey Company Parity fault locating means
US4360915A (en) * 1979-02-07 1982-11-23 The Warner & Swasey Company Error detection means
US4412327A (en) * 1981-02-25 1983-10-25 Western Electric Company, Inc. Test circuit for checking memory output state continuously during time window
US4528666A (en) * 1983-01-03 1985-07-09 Texas Instruments Incorporated Memory system with built in parity
US4593393A (en) * 1984-02-06 1986-06-03 Motorola, Inc. Quasi parallel cyclic redundancy checker
US4608669A (en) * 1984-05-18 1986-08-26 International Business Machines Corporation Self contained array timing
US4827476A (en) * 1987-04-16 1989-05-02 Tandem Computers Incorporated Scan test apparatus for digital systems having dynamic random access memory
JPS6489823A (en) * 1987-09-30 1989-04-05 Toshiba Corp Control circuit for radio equipment
JPH02260200A (ja) * 1989-03-30 1990-10-22 Sharp Corp 複数ビット並列テスト機能を有する半導体記憶装置における複数ビット並列機能テスト方法
US5951703A (en) * 1993-06-28 1999-09-14 Tandem Computers Incorporated System and method for performing improved pseudo-random testing of systems having multi driver buses
DE59308225D1 (de) * 1993-08-10 1998-04-09 Siemens Ag Verfahren zum Erkennen von Adressierungsfehlern bei Speichern für digitale binärcodierte Datenwörter
US5355377A (en) * 1993-11-23 1994-10-11 Tetra Assoc. Inc. Auto-selectable self-parity generator
SE502576C2 (sv) * 1993-11-26 1995-11-13 Ellemtel Utvecklings Ab Feltolerant kösystem
EP0744755A1 (en) * 1995-05-25 1996-11-27 International Business Machines Corporation Test method and device for embedded memories on semiconductor substrates
FR2751461B1 (fr) * 1996-07-22 1998-11-06 Sgs Thomson Microelectronics Dispositif de controle de finalite de test
US6134684A (en) * 1998-02-25 2000-10-17 International Business Machines Corporation Method and system for error detection in test units utilizing pseudo-random data
EP1026696B1 (en) * 1999-02-02 2005-07-06 Fujitsu Limited Test method and test circuit for electronic device
EP1031994B1 (en) 1999-02-23 2002-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Built-in self-test circuit for memory
DE69901534T2 (de) * 1999-02-23 2003-01-09 Taiwan Semiconductor Mfg. Co., Ltd. Integrierte Selbsttestschaltung für eine Speichereinrichtung
US8997255B2 (en) 2006-07-31 2015-03-31 Inside Secure Verifying data integrity in a data storage device
US8352752B2 (en) * 2006-09-01 2013-01-08 Inside Secure Detecting radiation-based attacks

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3727039A (en) * 1971-08-02 1973-04-10 Ibm Single select line storage system address check
US3719929A (en) * 1971-08-11 1973-03-06 Litton Systems Inc Memory analyzers
US3768071A (en) * 1972-01-24 1973-10-23 Ibm Compensation for defective storage positions
US3789204A (en) * 1972-06-06 1974-01-29 Honeywell Inf Systems Self-checking digital storage system
FR2257213A5 (it) * 1973-12-04 1975-08-01 Cii

Also Published As

Publication number Publication date
NL179097C (nl) 1986-07-01
NL7610819A (nl) 1977-04-13
DE2644733A1 (de) 1977-04-14
US4049956A (en) 1977-09-20
DE2644733C3 (de) 1979-03-29
DE2644733B2 (de) 1978-07-20
NL179097B (nl) 1986-02-03

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