FR2751461B1 - Dispositif de controle de finalite de test - Google Patents
Dispositif de controle de finalite de testInfo
- Publication number
- FR2751461B1 FR2751461B1 FR9609487A FR9609487A FR2751461B1 FR 2751461 B1 FR2751461 B1 FR 2751461B1 FR 9609487 A FR9609487 A FR 9609487A FR 9609487 A FR9609487 A FR 9609487A FR 2751461 B1 FR2751461 B1 FR 2751461B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- dysfunction
- lock
- test mode
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/006—Identification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9609487A FR2751461B1 (fr) | 1996-07-22 | 1996-07-22 | Dispositif de controle de finalite de test |
US08/897,869 US6055198A (en) | 1996-07-22 | 1997-07-21 | Device to check the end of a test |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9609487A FR2751461B1 (fr) | 1996-07-22 | 1996-07-22 | Dispositif de controle de finalite de test |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2751461A1 FR2751461A1 (fr) | 1998-01-23 |
FR2751461B1 true FR2751461B1 (fr) | 1998-11-06 |
Family
ID=9494564
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9609487A Expired - Fee Related FR2751461B1 (fr) | 1996-07-22 | 1996-07-22 | Dispositif de controle de finalite de test |
Country Status (2)
Country | Link |
---|---|
US (1) | US6055198A (fr) |
FR (1) | FR2751461B1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1817595B1 (fr) * | 2004-11-22 | 2009-03-04 | Freescale Semiconductor Inc. | Circuit integre et procede permettant de mettre en oeuvre un test securise |
KR102648785B1 (ko) * | 2017-01-11 | 2024-03-19 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 동작 방법 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1047437B (it) * | 1975-10-08 | 1980-09-10 | Cselt Centro Studi Lab Telecom | Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo |
JPS61292755A (ja) * | 1985-06-20 | 1986-12-23 | Fujitsu Ltd | 半導体集積回路 |
JPS6447972A (en) * | 1987-08-19 | 1989-02-22 | Nec Corp | Memory ic testing circuit |
JPH081760B2 (ja) * | 1987-11-17 | 1996-01-10 | 三菱電機株式会社 | 半導体記憶装置 |
EP0475588B1 (fr) * | 1990-08-17 | 1996-06-26 | STMicroelectronics, Inc. | Mémoire à semi-conducteur avec entrée de mode test empêchée pendant couple de démarrage |
JPH0612878A (ja) * | 1992-06-25 | 1994-01-21 | Mitsubishi Electric Corp | 半導体メモリ装置 |
JPH0676598A (ja) * | 1992-08-28 | 1994-03-18 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH07235200A (ja) * | 1994-02-24 | 1995-09-05 | Toshiba Corp | 半導体記憶装置 |
US5594694A (en) * | 1995-07-28 | 1997-01-14 | Micron Quantum Devices, Inc. | Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell |
US5642318A (en) * | 1995-12-05 | 1997-06-24 | Cypress Semicondcutor Corporation | Testing method for FIFOS |
-
1996
- 1996-07-22 FR FR9609487A patent/FR2751461B1/fr not_active Expired - Fee Related
-
1997
- 1997-07-21 US US08/897,869 patent/US6055198A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR2751461A1 (fr) | 1998-01-23 |
US6055198A (en) | 2000-04-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20080331 |