DE3580330D1 - Dynamisches ram in mos-technologie und verfahren zu seiner herstellung. - Google Patents

Dynamisches ram in mos-technologie und verfahren zu seiner herstellung.

Info

Publication number
DE3580330D1
DE3580330D1 DE8585302356T DE3580330T DE3580330D1 DE 3580330 D1 DE3580330 D1 DE 3580330D1 DE 8585302356 T DE8585302356 T DE 8585302356T DE 3580330 T DE3580330 T DE 3580330T DE 3580330 D1 DE3580330 D1 DE 3580330D1
Authority
DE
Germany
Prior art keywords
production
dynamic ram
mos technology
mos
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585302356T
Other languages
English (en)
Inventor
Mitsugi C O Patent Divis Ogura
Masaki C O Patent Div Momodomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3580330D1 publication Critical patent/DE3580330D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/911—Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/92—Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE8585302356T 1984-09-11 1985-04-03 Dynamisches ram in mos-technologie und verfahren zu seiner herstellung. Expired - Lifetime DE3580330D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59190002A JPH0793365B2 (ja) 1984-09-11 1984-09-11 半導体記憶装置およびその製造方法

Publications (1)

Publication Number Publication Date
DE3580330D1 true DE3580330D1 (de) 1990-12-06

Family

ID=16250744

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585302356T Expired - Lifetime DE3580330D1 (de) 1984-09-11 1985-04-03 Dynamisches ram in mos-technologie und verfahren zu seiner herstellung.

Country Status (4)

Country Link
US (1) US4630088A (de)
EP (1) EP0175433B1 (de)
JP (1) JPH0793365B2 (de)
DE (1) DE3580330D1 (de)

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US5208657A (en) * 1984-08-31 1993-05-04 Texas Instruments Incorporated DRAM Cell with trench capacitor and vertical channel in substrate
US4824793A (en) * 1984-09-27 1989-04-25 Texas Instruments Incorporated Method of making DRAM cell with trench capacitor
US4914739A (en) * 1984-10-31 1990-04-03 Texas Instruments, Incorporated Structure for contacting devices in three dimensional circuitry
US5102817A (en) * 1985-03-21 1992-04-07 Texas Instruments Incorporated Vertical DRAM cell and method
JPH0682800B2 (ja) * 1985-04-16 1994-10-19 株式会社東芝 半導体記憶装置
US5164917A (en) * 1985-06-26 1992-11-17 Texas Instruments Incorporated Vertical one-transistor DRAM with enhanced capacitance and process for fabricating
US5034785A (en) * 1986-03-24 1991-07-23 Siliconix Incorporated Planar vertical channel DMOS structure
JPS6334955A (ja) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
US4829017A (en) * 1986-09-25 1989-05-09 Texas Instruments Incorporated Method for lubricating a high capacity dram cell
US5124764A (en) * 1986-10-21 1992-06-23 Texas Instruments Incorporated Symmetric vertical MOS transistor with improved high voltage operation
JPS63114248A (ja) * 1986-10-31 1988-05-19 Texas Instr Japan Ltd 半導体集積回路装置
JPH0795568B2 (ja) * 1987-04-27 1995-10-11 日本電気株式会社 半導体記憶装置
US5109259A (en) * 1987-09-22 1992-04-28 Texas Instruments Incorporated Multiple DRAM cells in a trench
US4949138A (en) * 1987-10-27 1990-08-14 Texas Instruments Incorporated Semiconductor integrated circuit device
JPH01125858A (ja) * 1987-11-10 1989-05-18 Fujitsu Ltd 半導体装置およびその製造方法
JP2606857B2 (ja) * 1987-12-10 1997-05-07 株式会社日立製作所 半導体記憶装置の製造方法
JP2655859B2 (ja) * 1988-02-03 1997-09-24 株式会社日立製作所 半導体記憶装置
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US4958206A (en) * 1988-06-28 1990-09-18 Texas Instruments Incorporated Diffused bit line trench capacitor dram cell
US5225363A (en) * 1988-06-28 1993-07-06 Texas Instruments Incorporated Trench capacitor DRAM cell and method of manufacture
US5105245A (en) * 1988-06-28 1992-04-14 Texas Instruments Incorporated Trench capacitor DRAM cell with diffused bit lines adjacent to a trench
US4927779A (en) * 1988-08-10 1990-05-22 International Business Machines Corporation Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor
US5258635A (en) * 1988-09-06 1993-11-02 Kabushiki Kaisha Toshiba MOS-type semiconductor integrated circuit device
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US5192704A (en) * 1989-06-30 1993-03-09 Texas Instruments Incorporated Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell
US5136534A (en) * 1989-06-30 1992-08-04 Texas Instruments Incorporated Method and apparatus for a filament channel pass gate ferroelectric capacitor memory cell
US5276343A (en) * 1990-04-21 1994-01-04 Kabushiki Kaisha Toshiba Semiconductor memory device having a bit line constituted by a semiconductor layer
JPH0775247B2 (ja) * 1990-05-28 1995-08-09 株式会社東芝 半導体記憶装置
US5036020A (en) * 1990-08-31 1991-07-30 Texas Instrument Incorporated Method of fabricating microelectronic device incorporating capacitor having lowered topographical profile
US5087581A (en) * 1990-10-31 1992-02-11 Texas Instruments Incorporated Method of forming vertical FET device with low gate to source overlap capacitance
US5073519A (en) * 1990-10-31 1991-12-17 Texas Instruments Incorporated Method of fabricating a vertical FET device with low gate to drain overlap capacitance
JP2601022B2 (ja) * 1990-11-30 1997-04-16 日本電気株式会社 半導体装置の製造方法
KR940006679B1 (ko) * 1991-09-26 1994-07-25 현대전자산업 주식회사 수직형 트랜지스터를 갖는 dram셀 및 그 제조방법
US5158901A (en) * 1991-09-30 1992-10-27 Motorola, Inc. Field effect transistor having control and current electrodes positioned at a planar elevated surface and method of formation
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JP3311070B2 (ja) * 1993-03-15 2002-08-05 株式会社東芝 半導体装置
JPH06268173A (ja) * 1993-03-15 1994-09-22 Toshiba Corp 半導体記憶装置
DE4447730B4 (de) * 1993-03-15 2006-05-18 Kabushiki Kaisha Toshiba, Kawasaki Halbleiteranordnung mit Grabentypelementtrennbereich und Transistorstruktur
DE4327132C2 (de) * 1993-08-12 1997-01-23 Siemens Ag Dünnfilmtransistor und Verfahren zu dessen Herstellung
KR0147584B1 (ko) * 1994-03-17 1998-08-01 윤종용 매몰 비트라인 셀의 제조방법
JP3745392B2 (ja) 1994-05-26 2006-02-15 株式会社ルネサステクノロジ 半導体装置
DE19519160C1 (de) * 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
DE19519159C2 (de) * 1995-05-24 1998-07-09 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
JPH0982918A (ja) 1995-09-19 1997-03-28 Toshiba Corp 半導体記憶装置およびその製造方法
US6389582B1 (en) * 1995-12-21 2002-05-14 John Valainis Thermal driven placement
US5929476A (en) * 1996-06-21 1999-07-27 Prall; Kirk Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors
DE19720193C2 (de) * 1997-05-14 2002-10-17 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mindestens zwei vertikalen MOS-Transistoren und Verfahren zu deren Herstellung
US6337497B1 (en) * 1997-05-16 2002-01-08 International Business Machines Corporation Common source transistor capacitor stack
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US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US6528837B2 (en) * 1997-10-06 2003-03-04 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
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US6025225A (en) 1998-01-22 2000-02-15 Micron Technology, Inc. Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same
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US6124729A (en) * 1998-02-27 2000-09-26 Micron Technology, Inc. Field programmable logic arrays with vertical transistors
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Also Published As

Publication number Publication date
JPS6167953A (ja) 1986-04-08
EP0175433B1 (de) 1990-10-31
EP0175433A3 (en) 1986-12-30
JPH0793365B2 (ja) 1995-10-09
EP0175433A2 (de) 1986-03-26
US4630088A (en) 1986-12-16

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