DE3224287C2 - - Google Patents

Info

Publication number
DE3224287C2
DE3224287C2 DE3224287A DE3224287A DE3224287C2 DE 3224287 C2 DE3224287 C2 DE 3224287C2 DE 3224287 A DE3224287 A DE 3224287A DE 3224287 A DE3224287 A DE 3224287A DE 3224287 C2 DE3224287 C2 DE 3224287C2
Authority
DE
Germany
Prior art keywords
mos transistors
source
transistor
insulating film
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3224287A
Other languages
German (de)
English (en)
Other versions
DE3224287A1 (de
Inventor
Hideo Yokohama Jp Noguchi
Tugunari Kawasaki Jp Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP56100654A external-priority patent/JPS583265A/ja
Priority claimed from JP56100655A external-priority patent/JPS583266A/ja
Priority claimed from JP56100656A external-priority patent/JPS583267A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3224287A1 publication Critical patent/DE3224287A1/de
Application granted granted Critical
Publication of DE3224287C2 publication Critical patent/DE3224287C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Semiconductor Memories (AREA)
DE19823224287 1981-06-30 1982-06-28 Herstellungsverfahren fuer eine halbleitervorrichtung Granted DE3224287A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP56100654A JPS583265A (ja) 1981-06-30 1981-06-30 半導体装置の製造方法
JP56100655A JPS583266A (ja) 1981-06-30 1981-06-30 論理回路の製造方法
JP56100656A JPS583267A (ja) 1981-06-30 1981-06-30 論理回路の製造方法

Publications (2)

Publication Number Publication Date
DE3224287A1 DE3224287A1 (de) 1983-01-13
DE3224287C2 true DE3224287C2 (US06826419-20041130-M00005.png) 1988-04-28

Family

ID=27309273

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19823249828 Pending DE3249828A1 (US06826419-20041130-M00005.png) 1981-06-30 1982-06-28
DE19823224287 Granted DE3224287A1 (de) 1981-06-30 1982-06-28 Herstellungsverfahren fuer eine halbleitervorrichtung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE19823249828 Pending DE3249828A1 (US06826419-20041130-M00005.png) 1981-06-30 1982-06-28

Country Status (3)

Country Link
US (1) US4608748A (US06826419-20041130-M00005.png)
DE (2) DE3249828A1 (US06826419-20041130-M00005.png)
GB (1) GB2102623B (US06826419-20041130-M00005.png)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610089A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Method of fabrication of semiconductor integrated circuit device
IT1217372B (it) * 1988-03-28 1990-03-22 Sgs Thomson Microelectronics Procedimento per la programmazione di memorie rom in tecnologia mos ecmos
JP2509707B2 (ja) * 1989-09-04 1996-06-26 株式会社東芝 半導体装置の製造方法
JPH03266462A (ja) * 1990-03-16 1991-11-27 Toshiba Micro Electron Kk 半導体記憶装置
US5200355A (en) * 1990-12-10 1993-04-06 Samsung Electronics Co., Ltd. Method for manufacturing a mask read only memory device
DE69212897T2 (de) * 1991-05-20 1997-03-13 Matsushita Electronics Corp Herstellungsverfahren für MIS-Halbleiterbauelement
JP3132582B2 (ja) * 1991-07-12 2001-02-05 日本電気株式会社 半導体装置
KR940004609B1 (ko) * 1991-09-04 1994-05-25 삼성전자 주식회사 마스크 리드 온리 메모리
US5414221A (en) * 1991-12-31 1995-05-09 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
JP3202784B2 (ja) * 1992-04-13 2001-08-27 三菱電機株式会社 マスクｒｏｍ半導体装置およびその製造方法
US5354704A (en) * 1993-07-28 1994-10-11 United Microelectronics Corporation Symmetric SRAM cell with buried N+ local interconnection line
KR0135047B1 (ko) * 1994-06-30 1998-04-20 문정환 반도체 읽기 전용 기억 장치의 코딩 방법
US5512507A (en) * 1994-09-14 1996-04-30 United Microelectronics Corporation Process for post metal coding of a ROM, by gate etch
FR2730345B1 (fr) * 1995-02-03 1997-04-04 Matra Mhs Procede de fabrication d'une memoire morte en technologie mos, et memoire ainsi obtenue
US5773346A (en) * 1995-12-06 1998-06-30 Micron Technology, Inc. Semiconductor processing method of forming a buried contact
TW323397B (en) * 1996-10-02 1997-12-21 United Microelectronics Corp Multi-level read only memory structure and manufacturing method thereof
JP2000260886A (ja) * 1999-03-11 2000-09-22 Toshiba Corp 半導体記憶装置及びその製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2312413A1 (de) * 1972-03-10 1973-09-27 Matsushita Electronics Corp Verfahren zur herstellung von matrixkreisen mit in serie geschalteten gattern
DE2750209A1 (de) * 1976-12-14 1978-06-15 Standard Microsyst Smc Integrierte halbleiterschaltung und verfahren zu ihrer herstellung
DE2909197A1 (de) * 1978-03-20 1979-10-04 Texas Instruments Inc Verfahren zur herstellung eines festspeichers und festspeichermatrix
JPS563688B2 (US06826419-20041130-M00005.png) * 1976-12-14 1981-01-27
DE3036869A1 (de) * 1979-10-01 1981-04-16 Hitachi, Ltd., Tokyo Integrierte halbleiterschaltung, schaltungsprogrammiersystem und schaltungsprogrammierverfahren derselben

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969150A (en) * 1973-12-03 1976-07-13 Fairchild Camera And Instrument Corporation Method of MOS transistor manufacture
JPS5128551A (ja) * 1974-09-04 1976-03-10 Nippon Steel Corp Shitamukyosetsuhoho
JPS5232557A (en) * 1975-09-05 1977-03-11 Toshiba Corp Supply control device
US4151020A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated High density N-channel silicon gate read only memory
US4230504B1 (en) * 1978-04-27 1997-03-04 Texas Instruments Inc Method of making implant programmable N-channel rom
US4268950A (en) * 1978-06-05 1981-05-26 Texas Instruments Incorporated Post-metal ion implant programmable MOS read only memory
JPS559414A (en) * 1978-07-05 1980-01-23 Toshiba Corp Manufacturing method of semiconductor device
JPS599632B2 (ja) * 1979-06-25 1984-03-03 東ソー株式会社 電解槽
US4365405A (en) * 1981-05-28 1982-12-28 General Motors Corporation Method of late programming read only memory devices
US4397887A (en) * 1982-08-18 1983-08-09 National Semiconductor Corporation Postponed ROM programming

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2312413A1 (de) * 1972-03-10 1973-09-27 Matsushita Electronics Corp Verfahren zur herstellung von matrixkreisen mit in serie geschalteten gattern
DE2750209A1 (de) * 1976-12-14 1978-06-15 Standard Microsyst Smc Integrierte halbleiterschaltung und verfahren zu ihrer herstellung
JPS563688B2 (US06826419-20041130-M00005.png) * 1976-12-14 1981-01-27
DE2909197A1 (de) * 1978-03-20 1979-10-04 Texas Instruments Inc Verfahren zur herstellung eines festspeichers und festspeichermatrix
DE3036869A1 (de) * 1979-10-01 1981-04-16 Hitachi, Ltd., Tokyo Integrierte halbleiterschaltung, schaltungsprogrammiersystem und schaltungsprogrammierverfahren derselben

Also Published As

Publication number Publication date
US4608748A (en) 1986-09-02
DE3224287A1 (de) 1983-01-13
GB2102623B (en) 1985-04-11
GB2102623A (en) 1983-02-02
DE3249828A1 (US06826419-20041130-M00005.png) 1986-03-27

Similar Documents

Publication Publication Date Title
DE3224287C2 (US06826419-20041130-M00005.png)
DE3929129C2 (US06826419-20041130-M00005.png)
DE4434040C2 (de) Halbleiterspeichervorrichtung mit einer SOI-Struktur und Verfahren zur Herstellung derselben
DE4028488C2 (de) Verfahren zur Herstellung einer Halbleiterspeichervorrichtung
DE2814973A1 (de) Halbleiterspeichervorrichtung und verfahren zu ihrer herstellung
DE2756855A1 (de) Verfahren zum herstellen einer matrix aus speicherzellen mit hoher speicherkapazitaet
DE4318660C2 (de) Halbleitereinrichtung und Herstellungsverfahren dafür
DE2716691A1 (de) Feldeffekttransistor und verfahren zu dessen herstellung
DE4220497A1 (de) Halbleiterspeicherbauelement und verfahren zu dessen herstellung
DE2750209A1 (de) Integrierte halbleiterschaltung und verfahren zu ihrer herstellung
DE4332074A1 (de) Halbleiterspeichereinrichtung und Verfahren zu ihrer Herstellung
DE2852049A1 (de) Fest- oder lesespeicher
DE3685969T2 (de) Integrierte schaltung mit halbleiterkondensator und verfahren zu ihrer herstellung.
DE3109074C2 (US06826419-20041130-M00005.png)
DE4426311A1 (de) Leiterbahnstruktur eines Halbleiterbauelementes und Verfahren zu ihrer Herstellung
DE3543937C2 (US06826419-20041130-M00005.png)
DE3840559C2 (US06826419-20041130-M00005.png)
DE19824209A1 (de) Halbleitervorrichtung
DE3140268A1 (de) Halbleiteranordnung mit mindestens einem feldeffekttransistor und verfahren zu ihrer herstellung
DE4008883C2 (de) Nur-Lese-Speicher vom Maskentyp und Verfahren zu dessen Herstellung
DE2932928A1 (de) Verfahren zur herstellung von vlsi-schaltungen
DE4441153A1 (de) Verfahren zur Herstellung eines Kondensators einer Halbleiterspeichervorrichtung
DE4125199C2 (de) Kompakte Halbleiterspeicheranordnung, Verfahren zu deren Herstellung und Speichermatrix
DE19542240C2 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE3923619C2 (US06826419-20041130-M00005.png)

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8172 Supplementary division/partition in:

Ref country code: DE

Ref document number: 3249828

Format of ref document f/p: P

Q171 Divided out to:

Ref country code: DE

Ref document number: 3249828

8127 New person/name/address of the applicant

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

8128 New person/name/address of the agent

Representative=s name: EITLE, W., DIPL.-ING. HOFFMANN, K., DIPL.-ING. DR.

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee