DE3203825C2 - Signaldetektorschaltung - Google Patents

Signaldetektorschaltung

Info

Publication number
DE3203825C2
DE3203825C2 DE3203825A DE3203825A DE3203825C2 DE 3203825 C2 DE3203825 C2 DE 3203825C2 DE 3203825 A DE3203825 A DE 3203825A DE 3203825 A DE3203825 A DE 3203825A DE 3203825 C2 DE3203825 C2 DE 3203825C2
Authority
DE
Germany
Prior art keywords
circuit
line
signal
potential
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3203825A
Other languages
German (de)
English (en)
Other versions
DE3203825A1 (de
Inventor
Roger Green Neshanic Station N.J. Stewart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE3203825A1 publication Critical patent/DE3203825A1/de
Application granted granted Critical
Publication of DE3203825C2 publication Critical patent/DE3203825C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/061—Sense amplifier enabled by a address transition detection related control signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
DE3203825A 1981-02-06 1982-02-04 Signaldetektorschaltung Expired DE3203825C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/232,303 US4405996A (en) 1981-02-06 1981-02-06 Precharge with power conservation

Publications (2)

Publication Number Publication Date
DE3203825A1 DE3203825A1 (de) 1982-08-26
DE3203825C2 true DE3203825C2 (de) 1985-04-18

Family

ID=22872594

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3203825A Expired DE3203825C2 (de) 1981-02-06 1982-02-04 Signaldetektorschaltung

Country Status (7)

Country Link
US (1) US4405996A (cg-RX-API-DMAC7.html)
JP (1) JPS57152588A (cg-RX-API-DMAC7.html)
CA (1) CA1185372A (cg-RX-API-DMAC7.html)
DE (1) DE3203825C2 (cg-RX-API-DMAC7.html)
FR (1) FR2499747B1 (cg-RX-API-DMAC7.html)
GB (1) GB2092851B (cg-RX-API-DMAC7.html)
IT (1) IT1149703B (cg-RX-API-DMAC7.html)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589285A (ja) * 1981-07-08 1983-01-19 Toshiba Corp 半導体装置
JPS58128097A (ja) * 1981-12-29 1983-07-30 Fujitsu Ltd 半導体記憶装置
JPS5963094A (ja) * 1982-10-04 1984-04-10 Fujitsu Ltd メモリ装置
US4516123A (en) * 1982-12-27 1985-05-07 At&T Bell Laboratories Integrated circuit including logic array with distributed ground connections
JPS59178685A (ja) * 1983-03-30 1984-10-09 Toshiba Corp 半導体記憶回路
JPS59221891A (ja) * 1983-05-31 1984-12-13 Toshiba Corp スタテイツク型半導体記憶装置
US4567387A (en) * 1983-06-30 1986-01-28 Rca Corporation Linear sense amplifier
US4685087A (en) * 1983-08-31 1987-08-04 Texas Instruments Incorporated SRAM with constant pulse width
US4918658A (en) * 1983-08-31 1990-04-17 Texas Instruments Incorporated Static random access memory with asynchronous power-down
JPS60136086A (ja) * 1983-12-23 1985-07-19 Hitachi Ltd 半導体記憶装置
JPS60182096A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd 半導体記憶装置
US4710648A (en) * 1984-05-09 1987-12-01 Hitachi, Ltd. Semiconductor including signal processor and transient detector for low temperature operation
JPS6124091A (ja) * 1984-07-12 1986-02-01 Nec Corp メモリ回路
JPS6154098A (ja) * 1984-08-23 1986-03-18 Fujitsu Ltd パルス発生回路
US4598216A (en) * 1984-08-27 1986-07-01 Ncr Corporation Assist circuit for a data bus in a data processing system
JPS61196498A (ja) * 1985-02-26 1986-08-30 Mitsubishi Electric Corp 半導体記憶装置
US5051889A (en) * 1987-10-23 1991-09-24 Chips And Technologies, Incorporated Page interleaved memory access
US5187686A (en) * 1990-02-14 1993-02-16 Zilog, Inc. Control circuit having outputs with differing rise and fall times
US5239237A (en) * 1990-02-14 1993-08-24 Zilog, Inc. Control circuit having outputs with differing rise and fall times
GB2243232A (en) * 1990-04-06 1991-10-23 Mosaid Inc DRAM column address latching technique
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5280452A (en) * 1991-07-12 1994-01-18 International Business Machines Corporation Power saving semsing circuits for dynamic random access memory
KR100226266B1 (ko) * 1996-06-29 1999-10-15 김영환 반도체 메모리장치의 카스 버퍼회로

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3942162A (en) * 1974-07-01 1976-03-02 Motorola, Inc. Pre-conditioning circuits for MOS integrated circuits
JPS6057156B2 (ja) * 1978-05-24 1985-12-13 株式会社日立製作所 半導体メモリ装置
US4338679A (en) * 1980-12-24 1982-07-06 Mostek Corporation Row driver circuit for semiconductor memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NICHTS-ERMITTELT

Also Published As

Publication number Publication date
FR2499747A1 (fr) 1982-08-13
JPS57152588A (en) 1982-09-20
DE3203825A1 (de) 1982-08-26
FR2499747B1 (fr) 1986-04-04
JPS6221197B2 (cg-RX-API-DMAC7.html) 1987-05-11
GB2092851A (en) 1982-08-18
IT8219166A0 (it) 1982-01-18
US4405996A (en) 1983-09-20
IT1149703B (it) 1986-12-10
GB2092851B (en) 1985-07-24
CA1185372A (en) 1985-04-09

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee