DE3119886C2 - - Google Patents

Info

Publication number
DE3119886C2
DE3119886C2 DE3119886A DE3119886A DE3119886C2 DE 3119886 C2 DE3119886 C2 DE 3119886C2 DE 3119886 A DE3119886 A DE 3119886A DE 3119886 A DE3119886 A DE 3119886A DE 3119886 C2 DE3119886 C2 DE 3119886C2
Authority
DE
Germany
Prior art keywords
layer
single crystal
semiconductor layer
temperature
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3119886A
Other languages
German (de)
English (en)
Other versions
DE3119886A1 (de
Inventor
Yamichi Sagamihara Kanagawa Jp Ohmura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP6589780A external-priority patent/JPS56162828A/ja
Priority claimed from JP55143625A external-priority patent/JPS5768064A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3119886A1 publication Critical patent/DE3119886A1/de
Application granted granted Critical
Publication of DE3119886C2 publication Critical patent/DE3119886C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2921—Materials being crystalline insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3822—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
DE19813119886 1980-05-20 1981-05-19 Verfahren zur herstellung eines halbleiterbauelements Granted DE3119886A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6589780A JPS56162828A (en) 1980-05-20 1980-05-20 Manufacture of semiconductor device
JP55143625A JPS5768064A (en) 1980-10-16 1980-10-16 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
DE3119886A1 DE3119886A1 (de) 1982-03-11
DE3119886C2 true DE3119886C2 (enExample) 1989-08-24

Family

ID=26407068

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19813119886 Granted DE3119886A1 (de) 1980-05-20 1981-05-19 Verfahren zur herstellung eines halbleiterbauelements

Country Status (3)

Country Link
US (1) US4385937A (enExample)
DE (1) DE3119886A1 (enExample)
FR (1) FR2483127B1 (enExample)

Families Citing this family (63)

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JPS577924A (en) * 1980-06-18 1982-01-16 Hitachi Ltd Semiconductor device and manufacture thereof
JPS5856409A (ja) * 1981-09-30 1983-04-04 Toshiba Corp 半導体装置の製造方法
JPS5861622A (ja) * 1981-10-09 1983-04-12 Hitachi Ltd 単結晶薄膜の製造方法
FR2527385B1 (fr) * 1982-04-13 1987-05-22 Suwa Seikosha Kk Transistor a couche mince et panneau d'affichage a cristaux liquides utilisant ce type de transistor
JPS5978557A (ja) * 1982-10-27 1984-05-07 Toshiba Corp 相補型ｍｏｓ半導体装置の製造方法
US4509990A (en) * 1982-11-15 1985-04-09 Hughes Aircraft Company Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
JPS59159563A (ja) * 1983-03-02 1984-09-10 Toshiba Corp 半導体装置の製造方法
JPH077826B2 (ja) * 1983-08-25 1995-01-30 忠弘 大見 半導体集積回路
JPS60117613A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd 半導体装置の製造方法
US4588447A (en) * 1984-06-25 1986-05-13 Rockwell International Corporation Method of eliminating p-type electrical activity and increasing channel mobility of Si-implanted and recrystallized SOS films
CA1239706A (en) * 1984-11-26 1988-07-26 Hisao Hayashi Method of forming a thin semiconductor film
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4659392A (en) * 1985-03-21 1987-04-21 Hughes Aircraft Company Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits
US4751554A (en) * 1985-09-27 1988-06-14 Rca Corporation Silicon-on-sapphire integrated circuit and method of making the same
US4758529A (en) * 1985-10-31 1988-07-19 Rca Corporation Method of forming an improved gate dielectric for a MOSFET on an insulating substrate
US4722912A (en) * 1986-04-28 1988-02-02 Rca Corporation Method of forming a semiconductor structure
US4735917A (en) * 1986-04-28 1988-04-05 General Electric Company Silicon-on-sapphire integrated circuits
US4751561A (en) * 1986-04-29 1988-06-14 Rca Corporation Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a silicon wafer
US4755481A (en) * 1986-05-15 1988-07-05 General Electric Company Method of making a silicon-on-insulator transistor
JPS6310573A (ja) * 1986-07-02 1988-01-18 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4775641A (en) * 1986-09-25 1988-10-04 General Electric Company Method of making silicon-on-sapphire semiconductor devices
US4749660A (en) * 1986-11-26 1988-06-07 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making an article comprising a buried SiO2 layer
US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
US4786955A (en) * 1987-02-24 1988-11-22 General Electric Company Semiconductor device with source and drain depth extenders and a method of making the same
US4753895A (en) * 1987-02-24 1988-06-28 Hughes Aircraft Company Method of forming low leakage CMOS device on insulating substrate
US4999320A (en) * 1988-03-31 1991-03-12 Texas Instruments Incorporated Method for suppressing ionization avalanches in a helium wafer cooling assembly
US5290712A (en) * 1989-03-31 1994-03-01 Canon Kabushiki Kaisha Process for forming crystalline semiconductor film
US5137837A (en) * 1990-08-20 1992-08-11 Hughes Aircraft Company Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate
US7154147B1 (en) * 1990-11-26 2006-12-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US8106867B2 (en) 1990-11-26 2012-01-31 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US5602403A (en) * 1991-03-01 1997-02-11 The United States Of America As Represented By The Secretary Of The Navy Ion Implantation buried gate insulator field effect transistor
JPH06132303A (ja) * 1991-11-29 1994-05-13 Semiconductor Energy Lab Co Ltd 薄膜トランジスタおよびその作製方法
US5298434A (en) * 1992-02-07 1994-03-29 Harris Corporation Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits
US5643801A (en) * 1992-11-06 1997-07-01 Semiconductor Energy Laboratory Co., Ltd. Laser processing method and alignment
US6544825B1 (en) 1992-12-26 2003-04-08 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a MIS transistor
US5624582A (en) * 1993-01-21 1997-04-29 Vlsi Technology, Inc. Optimization of dry etching through the control of helium backside pressure
US5300443A (en) * 1993-06-30 1994-04-05 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating complementary enhancement and depletion mode field effect transistors on a single substrate
US6312968B1 (en) * 1993-06-30 2001-11-06 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating an electrically addressable silicon-on-sapphire light valve
US5572040A (en) * 1993-07-12 1996-11-05 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
US5930638A (en) * 1993-07-12 1999-07-27 Peregrine Semiconductor Corp. Method of making a low parasitic resistor on ultrathin silicon on insulator
US5864162A (en) * 1993-07-12 1999-01-26 Peregrine Seimconductor Corporation Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire
US5973363A (en) * 1993-07-12 1999-10-26 Peregrine Semiconductor Corp. CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator
US5863823A (en) * 1993-07-12 1999-01-26 Peregrine Semiconductor Corporation Self-aligned edge control in silicon on insulator
US5416043A (en) * 1993-07-12 1995-05-16 Peregrine Semiconductor Corporation Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer
US5973382A (en) * 1993-07-12 1999-10-26 Peregrine Semiconductor Corporation Capacitor on ultrathin semiconductor on insulator
JP3403812B2 (ja) * 1994-05-31 2003-05-06 株式会社半導体エネルギー研究所 薄膜トランジスタを用いた半導体装置の作製方法
US6133620A (en) * 1995-05-26 2000-10-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and process for fabricating the same
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
US5670387A (en) * 1995-01-03 1997-09-23 Motorola, Inc. Process for forming semiconductor-on-insulator device
GB9520901D0 (en) * 1995-10-12 1995-12-13 Philips Electronics Nv Electronic device manufacture
EP1019954B1 (en) * 1998-02-04 2013-05-15 Applied Materials, Inc. Method and apparatus for low-temperature annealing of electroplated copper micro-structures in the production of a microelectronic device
KR100487426B1 (ko) * 2001-07-11 2005-05-04 엘지.필립스 엘시디 주식회사 폴리실리콘 결정화방법 그리고, 이를 이용한 폴리실리콘박막트랜지스터의 제조방법 및 액정표시소자의 제조방법
JP4653374B2 (ja) * 2001-08-23 2011-03-16 セイコーエプソン株式会社 電気光学装置の製造方法
TWI261358B (en) * 2002-01-28 2006-09-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
US7749818B2 (en) 2002-01-28 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
TW200302511A (en) * 2002-01-28 2003-08-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
TWI267131B (en) * 2002-03-05 2006-11-21 Semiconductor Energy Lab Semiconductor element and semiconductor device using the same
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
JP4603845B2 (ja) * 2004-10-12 2010-12-22 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
EP1820005B1 (en) * 2004-11-24 2019-01-09 Sensirion Holding AG Method for applying selectively a layer to a structured substrate by the usage of a temperature gradient in the substrate
US7291539B2 (en) * 2005-06-01 2007-11-06 International Business Machines Corporation Amorphization/templated recrystallization method for hybrid orientation substrates
US7692223B2 (en) * 2006-04-28 2010-04-06 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method for manufacturing the same
US8324661B2 (en) * 2009-12-23 2012-12-04 Intel Corporation Quantum well transistors with remote counter doping

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US4177084A (en) * 1978-06-09 1979-12-04 Hewlett-Packard Company Method for producing a low defect layer of silicon-on-sapphire wafer
US4309225A (en) * 1979-09-13 1982-01-05 Massachusetts Institute Of Technology Method of crystallizing amorphous material with a moving energy beam
US4261762A (en) * 1979-09-14 1981-04-14 Eaton Corporation Method for conducting heat to or from an article being treated under vacuum

Also Published As

Publication number Publication date
DE3119886A1 (de) 1982-03-11
US4385937A (en) 1983-05-31
FR2483127B1 (fr) 1986-06-27
FR2483127A1 (fr) 1981-11-27

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: H01L 21/324

8126 Change of the secondary classification

Free format text: H01L 29/78 H01L 27/12 H01L 21/86 H01L 21/265 H01L 21/268

8128 New person/name/address of the agent

Representative=s name: KADOR, U., DIPL.-CHEM. DR.RER.NAT., PAT.-ANW., 800

8127 New person/name/address of the applicant

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee