JPS5768064A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5768064A
JPS5768064A JP55143625A JP14362580A JPS5768064A JP S5768064 A JPS5768064 A JP S5768064A JP 55143625 A JP55143625 A JP 55143625A JP 14362580 A JP14362580 A JP 14362580A JP S5768064 A JPS5768064 A JP S5768064A
Authority
JP
Japan
Prior art keywords
single crystal
substrate
film
channel element
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55143625A
Other languages
Japanese (ja)
Inventor
Kazumichi Omura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55143625A priority Critical patent/JPS5768064A/en
Priority to US06/263,502 priority patent/US4385937A/en
Priority to DE19813119886 priority patent/DE3119886A1/en
Priority to FR8110064A priority patent/FR2483127B1/en
Publication of JPS5768064A publication Critical patent/JPS5768064A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To enhance the integration of a C-MOS circuit by injecting Si ions on an n channel element forming region of an SOS substrate, converting the interior into amorphous state and then heating the surface temperature higher than the interior to form a single crystal, thereby enhancing the electron mobility parallel to the surface. CONSTITUTION:An Si single crystal film 22 of 0.7mum thick is epitaxially grown on the main surface of a sapphire substrate 21, a CVD SiO2 film 23 is accumulated in 0.5mum on the surface, and then the film 23 of an n channel element 24 is removed. Subsequently, the acceleration voltage is sequentially switched at five stages up to 140-700keV, Si ions are injected in 10<15>cm<-2>, to be converted into amorphous state to remain the single crystal layer 22 at the surface side of the n channel region 24 and at the substrate 21 side at the p channel region. Then, the back surface of the substrate is adhered to a stainless steel cooling base 32 and is inserted into an oven 31 at 900 deg.C, is heat treated while maintaining the back surface at approx. 300 deg.C, and is converted in amorphous layer to single crysta. Subsequently, a C- MOS circuit is formed, thereby reducing the compression strain of the single crystal film of the n channel element region or altering it to tensilbe strength to enhance the electron mobility, and enabling to form the circuit of the same performance in smaller area.
JP55143625A 1980-05-20 1980-10-16 Manufacture of semiconductor device Pending JPS5768064A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP55143625A JPS5768064A (en) 1980-10-16 1980-10-16 Manufacture of semiconductor device
US06/263,502 US4385937A (en) 1980-05-20 1981-05-14 Regrowing selectively formed ion amorphosized regions by thermal gradient
DE19813119886 DE3119886A1 (en) 1980-05-20 1981-05-19 METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT
FR8110064A FR2483127B1 (en) 1980-05-20 1981-05-20 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55143625A JPS5768064A (en) 1980-10-16 1980-10-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5768064A true JPS5768064A (en) 1982-04-26

Family

ID=15343098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55143625A Pending JPS5768064A (en) 1980-05-20 1980-10-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5768064A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223112A (en) * 1984-04-20 1985-11-07 Agency Of Ind Science & Technol Heat treatment device for semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223112A (en) * 1984-04-20 1985-11-07 Agency Of Ind Science & Technol Heat treatment device for semiconductor

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