DE69528798T2 - CMOS-Halbleiterbauelement und Herstellungsverfahren - Google Patents

CMOS-Halbleiterbauelement und Herstellungsverfahren

Info

Publication number
DE69528798T2
DE69528798T2 DE69528798T DE69528798T DE69528798T2 DE 69528798 T2 DE69528798 T2 DE 69528798T2 DE 69528798 T DE69528798 T DE 69528798T DE 69528798 T DE69528798 T DE 69528798T DE 69528798 T2 DE69528798 T2 DE 69528798T2
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
cmos semiconductor
cmos
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69528798T
Other languages
English (en)
Other versions
DE69528798D1 (de
Inventor
Hiroto Kawagoe
Tatsumi Shirasu
Shogo Kiyota
Norio Suzuki
Eiichi Yamada
Yuji Sugino
Manabu Kitano
Yoshihiko Sakurai
Takashi Naganuma
Hisashi Arakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE69528798D1 publication Critical patent/DE69528798D1/de
Publication of DE69528798T2 publication Critical patent/DE69528798T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
DE69528798T 1994-07-28 1995-06-23 CMOS-Halbleiterbauelement und Herstellungsverfahren Expired - Fee Related DE69528798T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP17687294 1994-07-28
JP6265529A JPH0897163A (ja) 1994-07-28 1994-10-28 半導体ウエハの製造方法、半導体ウエハ、半導体集積回路装置の製造方法および半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69528798D1 DE69528798D1 (de) 2002-12-19
DE69528798T2 true DE69528798T2 (de) 2003-08-14

Family

ID=26497627

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69528798T Expired - Fee Related DE69528798T2 (de) 1994-07-28 1995-06-23 CMOS-Halbleiterbauelement und Herstellungsverfahren

Country Status (8)

Country Link
US (5) US6043114A (de)
EP (1) EP0696062B1 (de)
JP (1) JPH0897163A (de)
KR (1) KR100377649B1 (de)
CN (1) CN1110073C (de)
DE (1) DE69528798T2 (de)
HK (1) HK1010768A1 (de)
TW (1) TW269052B (de)

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JPH11214533A (ja) * 1998-01-29 1999-08-06 Nec Corp 半導体装置の製造方法
US6423615B1 (en) * 1999-09-22 2002-07-23 Intel Corporation Silicon wafers for CMOS and other integrated circuits
US6358821B1 (en) * 2000-07-19 2002-03-19 Chartered Semiconductor Manufacturing Inc. Method of copper transport prevention by a sputtered gettering layer on backside of wafer
US6878595B2 (en) * 2003-01-27 2005-04-12 Full Circle Research, Inc. Technique for suppression of latchup in integrated circuits (ICS)
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
KR100514172B1 (ko) * 2004-01-19 2005-09-09 삼성전자주식회사 반도체 소자 형성방법
US20060049464A1 (en) * 2004-09-03 2006-03-09 Rao G R Mohan Semiconductor devices with graded dopant regions
JP4387291B2 (ja) * 2004-12-06 2009-12-16 パナソニック株式会社 横型半導体デバイスおよびその製造方法
JP4703364B2 (ja) * 2005-10-24 2011-06-15 株式会社東芝 半導体装置及びその製造方法
CN101777498A (zh) * 2010-01-12 2010-07-14 上海宏力半导体制造有限公司 带浅表外延层的外延片形成方法及其外延片
WO2015145292A1 (en) 2014-03-28 2015-10-01 Semiconductor Energy Laboratory Co., Ltd. Transistor and semiconductor device
CN106653599B (zh) * 2015-11-02 2021-03-16 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
CN113381286B (zh) * 2021-06-02 2023-03-03 山东大学 离子束增强腐蚀制备晶体薄膜的方法

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JPS5617011A (en) * 1979-07-23 1981-02-18 Toshiba Corp Semiconductor device and manufacture thereof
US4684971A (en) * 1981-03-13 1987-08-04 American Telephone And Telegraph Company, At&T Bell Laboratories Ion implanted CMOS devices
JPS58218159A (ja) * 1982-06-11 1983-12-19 Toshiba Corp 相補型ｍｏｓ半導体装置
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
DE3314450A1 (de) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
JPS60132358A (ja) * 1983-12-20 1985-07-15 Nec Corp 相補型ｍｏｓ集積回路装置
JPS612356A (ja) * 1984-06-14 1986-01-08 Toshiba Corp Ｃｍｏｓ型半導体装置
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DE3662627D1 (en) * 1985-06-03 1989-05-03 Siemens Ag Method of simultaneously producing bipolar and complementary mos transistors as a common silicon substrate
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DE3765844D1 (de) * 1986-06-10 1990-12-06 Siemens Ag Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen.
EP0250722A3 (de) * 1986-07-04 1988-08-03 Siemens Aktiengesellschaft Verfahren zur Herstellung benachbarter, mit Dotierstoffionen unterschiedlichen Leitungstyps implantierter Wannen für hochintegrierte CMOS-Bauelemente
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JPH07114241B2 (ja) 1986-10-20 1995-12-06 松下電子工業株式会社 半導体装置
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IT1230028B (it) * 1988-12-16 1991-09-24 Sgs Thomson Microelectronics Procedimento di fabbricazione di dispositivi semiconduttori mos avvalentesi di un trattamento "gettering" di migliorare caratteristiche, e dispositivi semiconduttori mos con esso ottenuti
US5216269A (en) * 1989-03-31 1993-06-01 U.S. Philips Corp. Electrically-programmable semiconductor memories with buried injector region
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US5248624A (en) * 1991-08-23 1993-09-28 Exar Corporation Method of making isolated vertical pnp transistor in a complementary bicmos process with eeprom memory
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JPH0897163A (ja) * 1994-07-28 1996-04-12 Hitachi Ltd 半導体ウエハの製造方法、半導体ウエハ、半導体集積回路装置の製造方法および半導体集積回路装置
JP3637651B2 (ja) * 1995-03-22 2005-04-13 株式会社デンソー 温度式膨張弁

Also Published As

Publication number Publication date
EP0696062A3 (de) 1996-12-11
KR960005769A (ko) 1996-02-23
HK1010768A1 (en) 1999-06-25
US6630375B2 (en) 2003-10-07
US6806130B2 (en) 2004-10-19
US20020055204A1 (en) 2002-05-09
US6368905B1 (en) 2002-04-09
CN1110073C (zh) 2003-05-28
EP0696062A2 (de) 1996-02-07
DE69528798D1 (de) 2002-12-19
TW269052B (en) 1996-01-21
US6043114A (en) 2000-03-28
KR100377649B1 (ko) 2003-06-02
US20040219727A1 (en) 2004-11-04
EP0696062B1 (de) 2002-11-13
CN1121643A (zh) 1996-05-01
US20020061615A1 (en) 2002-05-23
JPH0897163A (ja) 1996-04-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee