DE2844762A1 - Dynamische speicherzelle - Google Patents

Dynamische speicherzelle

Info

Publication number
DE2844762A1
DE2844762A1 DE19782844762 DE2844762A DE2844762A1 DE 2844762 A1 DE2844762 A1 DE 2844762A1 DE 19782844762 DE19782844762 DE 19782844762 DE 2844762 A DE2844762 A DE 2844762A DE 2844762 A1 DE2844762 A1 DE 2844762A1
Authority
DE
Germany
Prior art keywords
layer
zone
memory cell
substrate
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19782844762
Other languages
German (de)
English (en)
Inventor
Amr M Mohsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of DE2844762A1 publication Critical patent/DE2844762A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
DE19782844762 1977-10-13 1978-10-13 Dynamische speicherzelle Withdrawn DE2844762A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84173577A 1977-10-13 1977-10-13

Publications (1)

Publication Number Publication Date
DE2844762A1 true DE2844762A1 (de) 1979-04-19

Family

ID=25285575

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782844762 Withdrawn DE2844762A1 (de) 1977-10-13 1978-10-13 Dynamische speicherzelle

Country Status (4)

Country Link
JP (1) JPS5465489A (enExample)
DE (1) DE2844762A1 (enExample)
FR (1) FR2406286A1 (enExample)
GB (2) GB2095901B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855079A1 (de) * 1978-12-20 1980-07-17 Siemens Ag Halbleiter-speicherschaltung
DE3102175A1 (de) 1980-01-25 1982-01-14 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleiter-speichervorrichtung

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2060997A (en) * 1978-01-03 1981-05-07 Erb D M Stratified charge memory divide
US4335450A (en) * 1980-01-30 1982-06-15 International Business Machines Corporation Non-destructive read out field effect transistor memory cell system
CN113363323B (zh) * 2020-03-05 2023-08-18 苏州大学 单栅场效应晶体管器件及调控其驱动电流的方法
KR20230165567A (ko) 2022-05-27 2023-12-05 삼성전자주식회사 반도체 메모리 소자 및 그 제조방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740731A (en) * 1971-08-02 1973-06-19 Texas Instruments Inc One transistor dynamic memory cell
GB1412132A (en) * 1972-10-10 1975-10-29 Texas Instruments Inc Dynamic data storage cell
CA1030263A (en) * 1973-05-21 1978-04-25 James A. Marley (Jr.) Single bipolar transistor memory cell and method
FR2326761A1 (fr) * 1975-09-30 1977-04-29 Siemens Ag Memoire d'informations pour la memorisation d'informations sous forme de porteurs de charge electriques et procede pour sa mise en oeuvre
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855079A1 (de) * 1978-12-20 1980-07-17 Siemens Ag Halbleiter-speicherschaltung
DE3102175A1 (de) 1980-01-25 1982-01-14 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleiter-speichervorrichtung
DE3153137C2 (enExample) * 1980-01-25 1989-11-02 Kabushiki Kaisha Toshiba, Kawasaki, Kanagawa, Jp

Also Published As

Publication number Publication date
GB2006523B (en) 1982-12-01
GB2095901A (en) 1982-10-06
JPS5465489A (en) 1979-05-26
FR2406286A1 (fr) 1979-05-11
GB2006523A (en) 1979-05-02
FR2406286B1 (enExample) 1983-04-15
GB2095901B (en) 1983-02-23

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee