GB2006523A - Dynamic RAM memory and vertical charge coupled dynamic storage cell therefor - Google Patents

Dynamic RAM memory and vertical charge coupled dynamic storage cell therefor

Info

Publication number
GB2006523A
GB2006523A GB7839260A GB7839260A GB2006523A GB 2006523 A GB2006523 A GB 2006523A GB 7839260 A GB7839260 A GB 7839260A GB 7839260 A GB7839260 A GB 7839260A GB 2006523 A GB2006523 A GB 2006523A
Authority
GB
United Kingdom
Prior art keywords
cell
ram memory
vertical charge
storage cell
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7839260A
Other versions
GB2006523B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mohsen A M
Original Assignee
Mohsen A M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mohsen A M filed Critical Mohsen A M
Publication of GB2006523A publication Critical patent/GB2006523A/en
Application granted granted Critical
Publication of GB2006523B publication Critical patent/GB2006523B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

A dynamic RAM memory comprises a plurality of storage cells, each cell having its elements vertically stacked and using vertical charge coupling for charging and discharging the cell capacitor. The cell comprises a semiconductive body 10/13 having a buried channel 12 of opposite impurity concentration to that of the body 10/13 for forming the bit line of the memory. A thin insulator 15 is disposed on the surface of the body with a conductive strip 16 deposited thereon which form the word line of the memory. The thickness of the epitaxial layer, the impurity concentration of the buried channel and the epitaxial layer, together with the applied voltages, are selected for charge coupling operations during the reading and writing of information in the cell with no cross coupling between adjacent cells. Several embodiments are described, using epitaxial or multiply-diffused or implanted structures. <IMAGE>
GB7839260A 1977-10-13 1978-10-04 Dynamic ram memory and vertical charge coupled dynamic storage cell therefor Expired GB2006523B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84173577A 1977-10-13 1977-10-13

Publications (2)

Publication Number Publication Date
GB2006523A true GB2006523A (en) 1979-05-02
GB2006523B GB2006523B (en) 1982-12-01

Family

ID=25285575

Family Applications (2)

Application Number Title Priority Date Filing Date
GB7839260A Expired GB2006523B (en) 1977-10-13 1978-10-04 Dynamic ram memory and vertical charge coupled dynamic storage cell therefor
GB8136432A Expired GB2095901B (en) 1977-10-13 1978-10-04 An mos transistor

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB8136432A Expired GB2095901B (en) 1977-10-13 1978-10-04 An mos transistor

Country Status (4)

Country Link
JP (1) JPS5465489A (en)
DE (1) DE2844762A1 (en)
FR (1) FR2406286A1 (en)
GB (2) GB2006523B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0007910A1 (en) * 1978-01-03 1980-02-06 ERB, Darrell, M. A stratified charge memory device
FR2444991A1 (en) * 1978-12-20 1980-07-18 Siemens Ag SEMICONDUCTOR MEMORY CIRCUIT
EP0034244A2 (en) * 1980-01-30 1981-08-26 International Business Machines Corporation Non-destructive read-out one-FET cell memory matrix
EP4283681A1 (en) * 2022-05-27 2023-11-29 Samsung Electronics Co., Ltd. Semiconductor memory device and method of manufacture

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2070329B (en) 1980-01-25 1983-10-26 Tokyo Shibaura Electric Co Semiconductor memory device
CN113363323B (en) * 2020-03-05 2023-08-18 苏州大学 Single gate field effect transistor device and method for regulating and controlling driving current thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740731A (en) * 1971-08-02 1973-06-19 Texas Instruments Inc One transistor dynamic memory cell
GB1412132A (en) * 1972-10-10 1975-10-29 Texas Instruments Inc Dynamic data storage cell
CA1030263A (en) * 1973-05-21 1978-04-25 James A. Marley (Jr.) Single bipolar transistor memory cell and method
FR2326761A1 (en) * 1975-09-30 1977-04-29 Siemens Ag MEMORY OF INFORMATION FOR STORING INFORMATION IN THE FORM OF ELECTRIC CHARGERS AND PROCESS FOR ITS IMPLEMENTATION
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0007910A1 (en) * 1978-01-03 1980-02-06 ERB, Darrell, M. A stratified charge memory device
EP0007910A4 (en) * 1978-01-03 1980-11-28 Darrell M Erb A stratified charge memory device.
FR2444991A1 (en) * 1978-12-20 1980-07-18 Siemens Ag SEMICONDUCTOR MEMORY CIRCUIT
EP0034244A2 (en) * 1980-01-30 1981-08-26 International Business Machines Corporation Non-destructive read-out one-FET cell memory matrix
EP0034244A3 (en) * 1980-01-30 1981-09-16 International Business Machines Corporation Non-destructive read-out one-fet cell memory matrix
EP4283681A1 (en) * 2022-05-27 2023-11-29 Samsung Electronics Co., Ltd. Semiconductor memory device and method of manufacture

Also Published As

Publication number Publication date
GB2095901B (en) 1983-02-23
FR2406286A1 (en) 1979-05-11
DE2844762A1 (en) 1979-04-19
FR2406286B1 (en) 1983-04-15
GB2095901A (en) 1982-10-06
GB2006523B (en) 1982-12-01
JPS5465489A (en) 1979-05-26

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee