GB1412132A - Dynamic data storage cell - Google Patents

Dynamic data storage cell

Info

Publication number
GB1412132A
GB1412132A GB4658772A GB4658772A GB1412132A GB 1412132 A GB1412132 A GB 1412132A GB 4658772 A GB4658772 A GB 4658772A GB 4658772 A GB4658772 A GB 4658772A GB 1412132 A GB1412132 A GB 1412132A
Authority
GB
United Kingdom
Prior art keywords
voltage
stored
row
switch
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4658772A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to GB4658772A priority Critical patent/GB1412132A/en
Publication of GB1412132A publication Critical patent/GB1412132A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)

Abstract

1412132 Semi-conductor matrix stores TEXAS INSTRUMENTS Inc (P M Frandon) 10 Oct 1972 46587/72 Heading G4C [Also in Division H1] An integrated matrix of IGFET storage cells for use in a dynamic random access memory comprises a grounded wafer of P type silicon with parallel interleaved N + and P + strips 70, 74 (Fig. 5) formed by diffusion in one face and further N+ regions 76 individual to each cell each overlying part of a P + strip and having a portion 76a extending beyond the strip towards the adjacent N + strip. Strip 70 constitutes the drain regions of all the transistors in a column while regions 76 constitute the sources, the junction capacitances of which are enhanced by the heavy doping of strips 74. A layer of insulation 80 of silicon dioxide and/or nitride is 500 Š thick over the IGFET channels 78 and 10,000 Š thick elsewhere. Each row conductor 82 which may be of aluminium or silicon runs normal to the strips and forms the gate of all transistors in the row. One cycle of operation of the memory is as follows: A refresh cycle is initiated by applying clock pulse # 1 to switch on transistors Q 3 and Q 2 (Fig. 2) thus switching off transistor Q 4 by grounding its gate and connecting supply voltage V DD to the respective column data line input line Bj. Termination of the pulse leaves Bj at this voltage and the gate of transistor Q 4 at ground. Row enable line Xi is then brought to a high voltage to couple the cells in its row to the column. Considering a particular cell, if its source capacitance is charged (logic 1) it remains charged and Bj remains at the same voltage whereas if it is discharged (logic 0) it recharges and since its capacitance equals that of Bj the potential at 32 is halved causing Q 2 to switch off. On application of clock pulse # 2 to switch on Q 1 V DD is grounded via Q 2 if a logic 1 is stored and Q 4 remains off and the voltage on Bj refreshes the stored charge whereas if logic 0 is stored Q 4 is on thus grounding line Bj to refresh the stored 0. The same procedure is used for each row. To read out information the voltage on row data line Xi is again raised, the appropriate column data line Bj selected by switching on transistor Q 6 . If a 0 is stored, since Q 4 is on a circuit to earth is completed via Q 4 , Q 5 and Q 6 and load resistor R 0 , but if a 1 is stored Q 4 is off and no current flows in Ro. Information is then written in by applying an enable pulse WE to switch on transistor Q 8 . If a 1 is already stored, since Bj is not grounded data is written by application of the appropriate voltage via Q 8 . If a 0 is stored Bj is grounded but a 1 may be written by application of a sufficient voltage via Q 8 since the voltage drop in Q 4 causes Q 2 and thus Q 4 itself to switch off thereby raising Bj to the applied voltage to charge the cell. Any suitable decoding circuits may be used with the matrix but a preferred circuit is described (Figs. 6a and 6b, not shown).
GB4658772A 1972-10-10 1972-10-10 Dynamic data storage cell Expired GB1412132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB4658772A GB1412132A (en) 1972-10-10 1972-10-10 Dynamic data storage cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4658772A GB1412132A (en) 1972-10-10 1972-10-10 Dynamic data storage cell

Publications (1)

Publication Number Publication Date
GB1412132A true GB1412132A (en) 1975-10-29

Family

ID=10441842

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4658772A Expired GB1412132A (en) 1972-10-10 1972-10-10 Dynamic data storage cell

Country Status (1)

Country Link
GB (1) GB1412132A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2711523A1 (en) * 1976-03-16 1977-10-06 Tokyo Shibaura Electric Co SEMICONDUCTOR STORAGE DEVICE
FR2406286A1 (en) * 1977-10-13 1979-05-11 Mohsen Amr SEMICONDUCTOR MEMORY WITH DYNAMIC DIRECT ACCESS AND DYNAMIC CELL WITH VERTICAL LOAD TRANSFER FOR SUCH A MEMORY

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2711523A1 (en) * 1976-03-16 1977-10-06 Tokyo Shibaura Electric Co SEMICONDUCTOR STORAGE DEVICE
FR2406286A1 (en) * 1977-10-13 1979-05-11 Mohsen Amr SEMICONDUCTOR MEMORY WITH DYNAMIC DIRECT ACCESS AND DYNAMIC CELL WITH VERTICAL LOAD TRANSFER FOR SUCH A MEMORY

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PE20 Patent expired after termination of 20 years