DE2219696C3 - Verfarhen zum Herstellen einer monolithisch integrierten Halbleiteranordnung - Google Patents

Verfarhen zum Herstellen einer monolithisch integrierten Halbleiteranordnung

Info

Publication number
DE2219696C3
DE2219696C3 DE2219696A DE2219696A DE2219696C3 DE 2219696 C3 DE2219696 C3 DE 2219696C3 DE 2219696 A DE2219696 A DE 2219696A DE 2219696 A DE2219696 A DE 2219696A DE 2219696 C3 DE2219696 C3 DE 2219696C3
Authority
DE
Germany
Prior art keywords
field effect
effect transistors
substrate
transistors
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2219696A
Other languages
German (de)
English (en)
Other versions
DE2219696B2 (de
DE2219696A1 (de
Inventor
Madhukar Bhavanidas Beacon N.Y. Vora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2219696A1 publication Critical patent/DE2219696A1/de
Publication of DE2219696B2 publication Critical patent/DE2219696B2/de
Application granted granted Critical
Publication of DE2219696C3 publication Critical patent/DE2219696C3/de
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0107Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Element Separation (AREA)
DE2219696A 1971-04-28 1972-04-21 Verfarhen zum Herstellen einer monolithisch integrierten Halbleiteranordnung Expired DE2219696C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13816171A 1971-04-28 1971-04-28

Publications (3)

Publication Number Publication Date
DE2219696A1 DE2219696A1 (de) 1972-11-16
DE2219696B2 DE2219696B2 (de) 1978-04-06
DE2219696C3 true DE2219696C3 (de) 1982-02-18

Family

ID=22480723

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2219696A Expired DE2219696C3 (de) 1971-04-28 1972-04-21 Verfarhen zum Herstellen einer monolithisch integrierten Halbleiteranordnung

Country Status (12)

Country Link
JP (1) JPS5037507B1 (es)
AU (1) AU459156B2 (es)
CA (1) CA966231A (es)
CH (1) CH536029A (es)
DE (1) DE2219696C3 (es)
ES (2) ES402165A1 (es)
FR (1) FR2134360B1 (es)
GB (1) GB1358612A (es)
IT (1) IT947674B (es)
NL (1) NL7204804A (es)
SE (1) SE384949B (es)
ZA (1) ZA721782B (es)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3545040A1 (de) * 1984-12-20 1986-06-26 Sgs Microelettronica S.P.A., Catania Verfahren zur herstellung einer vergrabenen schicht und einer kollektorzone in einer monolithischen halbleitervorrichtung
DE3736369A1 (de) * 1986-11-04 1988-05-11 Samsung Semiconductor Tele Verfahren zur herstellung eines bicmos-bauelements

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2608267A1 (de) * 1976-02-28 1977-09-08 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer monolithisch integrierten schaltung
JPS5851561A (ja) * 1981-09-24 1983-03-26 Hitachi Ltd 半導体集積回路装置
JPS58225663A (ja) * 1982-06-23 1983-12-27 Toshiba Corp 半導体装置の製造方法
JPS5955052A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体集積回路装置の製造方法
JPS59177960A (ja) * 1983-03-28 1984-10-08 Hitachi Ltd 半導体装置およびその製造方法
US4727046A (en) * 1986-07-16 1988-02-23 Fairchild Semiconductor Corporation Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293087A (en) * 1963-03-05 1966-12-20 Fairchild Camera Instr Co Method of making isolated epitaxial field-effect device
US3481801A (en) * 1966-10-10 1969-12-02 Frances Hugle Isolation technique for integrated circuits
US3479233A (en) * 1967-01-16 1969-11-18 Ibm Method for simultaneously forming a buried layer and surface connection in semiconductor devices
US3447046A (en) * 1967-05-31 1969-05-27 Westinghouse Electric Corp Integrated complementary mos type transistor structure and method of making same
GB1280022A (en) * 1968-08-30 1972-07-05 Mullard Ltd Improvements in and relating to semiconductor devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3545040A1 (de) * 1984-12-20 1986-06-26 Sgs Microelettronica S.P.A., Catania Verfahren zur herstellung einer vergrabenen schicht und einer kollektorzone in einer monolithischen halbleitervorrichtung
DE3545040C2 (de) * 1984-12-20 1995-07-20 Sgs Microelettronica Spa Verfahren zur Herstellung einer vergrabenen Schicht und einer Kollektorzone in einer monolithischen Halbleitervorrichtung
DE3736369A1 (de) * 1986-11-04 1988-05-11 Samsung Semiconductor Tele Verfahren zur herstellung eines bicmos-bauelements

Also Published As

Publication number Publication date
FR2134360A1 (es) 1972-12-08
AU459156B2 (en) 1975-03-20
DE2219696B2 (de) 1978-04-06
ES402164A1 (es) 1975-03-01
NL7204804A (es) 1972-10-31
SE384949B (sv) 1976-05-24
ES402165A1 (es) 1975-03-16
JPS5037507B1 (es) 1975-12-03
CA966231A (en) 1975-04-15
DE2219696A1 (de) 1972-11-16
GB1358612A (en) 1974-07-03
ZA721782B (en) 1973-10-31
CH536029A (de) 1973-04-15
AU4164272A (en) 1973-12-20
FR2134360B1 (es) 1974-06-28
IT947674B (it) 1973-05-30

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee