DE19928981B4 - Vorrichtung und Verfahren zum Testen von Halbleiterspeichern - Google Patents

Vorrichtung und Verfahren zum Testen von Halbleiterspeichern Download PDF

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Publication number
DE19928981B4
DE19928981B4 DE19928981A DE19928981A DE19928981B4 DE 19928981 B4 DE19928981 B4 DE 19928981B4 DE 19928981 A DE19928981 A DE 19928981A DE 19928981 A DE19928981 A DE 19928981A DE 19928981 B4 DE19928981 B4 DE 19928981B4
Authority
DE
Germany
Prior art keywords
test
pattern
signal
semiconductor memory
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19928981A
Other languages
German (de)
English (en)
Other versions
DE19928981A1 (de
Inventor
Jun Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE19928981A1 publication Critical patent/DE19928981A1/de
Application granted granted Critical
Publication of DE19928981B4 publication Critical patent/DE19928981B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928—Formatter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE19928981A 1998-06-24 1999-06-24 Vorrichtung und Verfahren zum Testen von Halbleiterspeichern Expired - Fee Related DE19928981B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10-176777 1998-06-24
JP17677798 1998-06-24

Publications (2)

Publication Number Publication Date
DE19928981A1 DE19928981A1 (de) 2000-01-13
DE19928981B4 true DE19928981B4 (de) 2006-07-13

Family

ID=16019663

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19928981A Expired - Fee Related DE19928981B4 (de) 1998-06-24 1999-06-24 Vorrichtung und Verfahren zum Testen von Halbleiterspeichern

Country Status (2)

Country Link
KR (1) KR100295250B1 (ko)
DE (1) DE19928981B4 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10034855B4 (de) * 2000-07-18 2006-05-11 Infineon Technologies Ag System zum Test von schnellen integrierten Digitalschaltungen und BOST-Halbleiterschaltungsbaustein als Testschaltkreis
DE10034900C2 (de) 2000-07-18 2002-07-18 Infineon Technologies Ag System zum Test schneller synchroner Digitalschaltungen, insbesondere Halbleiterspeicherbausteinen
KR100618870B1 (ko) * 2004-10-23 2006-08-31 삼성전자주식회사 데이터 트레이닝 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996029649A1 (en) * 1995-03-17 1996-09-26 Aehr Test Systems Method and system for testing memory programming devices
DE69810489T2 (de) * 1997-09-09 2003-10-30 Teradyne Inc Kostengünstiges, hochparalleles speicherprüfgerät

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996029649A1 (en) * 1995-03-17 1996-09-26 Aehr Test Systems Method and system for testing memory programming devices
DE69810489T2 (de) * 1997-09-09 2003-10-30 Teradyne Inc Kostengünstiges, hochparalleles speicherprüfgerät

Also Published As

Publication number Publication date
DE19928981A1 (de) 2000-01-13
KR100295250B1 (ko) 2001-07-12
KR20000006389A (ko) 2000-01-25

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee