DE19928981B4 - Apparatus and method for testing semiconductor memories - Google Patents

Abstract

Semiconductor memory tester with
a pattern generator (PG) for outputting pattern data for generating a test pattern signal, an address signal and a control signal to be applied to a plurality of semiconductor memories to be tested, and an expected value pattern (EXP), wherein each of the semiconductor memories is a synchronous semiconductor memory having a semiconductor memory Can output clock for re-timing the output time of the data read from the respective semiconductor memory,
waveform generating means (WF) for converting the pattern data output from the pattern generator (PG) into the test pattern signal, the address signal and the control signal, each having a real waveform;
a logical comparator (LC) for comparing the data read from each one of the semiconductor memories to be tested with the expected value pattern (EXP) output by the pattern generator for determining whether the respective semiconductor memory under test is faulty or not;
phase measuring means (CP) for measuring the phase of a clock outputted from each of the plurality of semiconductor memories to be tested before starting the test of the ...

Description

The The present invention relates to a device and a Method for testing semiconductor memories, the semiconductor integrated circuits contain (often referred to as IC memory). In particular, it concerns the invention a semiconductor memory test apparatus and a semiconductor memory test method, the simultaneous testing of a plurality of each with high Speed operable memories are suitable.

In the not previously published WO 99/013475 describes a semiconductor memory tester which has a plurality of of semiconductor memories can test at the same time. The semiconductor memory test apparatus comprises a Pattern generator and a signal branching device for applying the Pattern signals to the semiconductor memory. Another signal branching circuit controls the feeder the read out of the semiconductor memory test signals to a Error processor. Furthermore, there is a delay circuit the signal propagation delays compensated within the test field containing the semiconductor memory.

Out WO 96/29649 discloses a semiconductor memory test device, for parallel testing of a plurality of semiconductor memories is designed and a compensation circuit for the compensation of Signal propagation delays within the test field receiving the semiconductor memory. The Semiconductor memory tester further comprises a pattern generator and an evaluation circuit for function evaluation of the tested semiconductor memories.

The enclosed 3 FIG. 15 shows an example of a conventional semiconductor memory test apparatus that can simultaneously test a plurality of semiconductor memories. This semiconductor memory test apparatus includes a pattern generator PG, a timing generator TG, a waveform generator WF, a driver circuit group DR, a level comparator group LVC, and a plurality of logic comparators LC. In the in 3 In the case shown, the semiconductor memory test apparatus is designed to simultaneously test three semiconductor memories MUT1, MUT2 and MUT3, the driver circuit group DR being formed by three driver groups and the level comparator group LVC having three comparator groups. Furthermore, three logical comparators LC are provided.

Of the Pattern generator PG and the timing generator TG are through a main controller (not shown) controlled in general is formed by a computer system and in the one of a user generated test program is loaded. The main controller controls the pattern generator PG and the timing generator TG mainly according to the test program. Of the Timing generator TG contains generally a period generator, a clock generator and a clock control circuit.

First, be different before starting the test of a semiconductor memory Data in the predetermined components of the test device of the Main controller set. After setting the data the semiconductor memory test is started. The pattern generator PG is done by applying a test start command from the main controller activated in the operating state and generates pattern data in accordance with the test program provided by the main controller.

From The pattern data PTN generated in the pattern generator PG is sent to the waveform generator WF created based on the pattern data and one of the Timing generator TG provided timing signal TS is a test pattern signal, an address signal and a control signal generated, each one real, to the three in the test Semiconductor memory (also referred to below as the memory under test MUT1, MUT2 and MUT3 have to be applied. During one Test pattern writing cycle in which a test pattern signal is converted into an in Test stored memory controls the control signal the operation of the memory under test in the write state. By the address signal in each case the memory cell is designated, in which the test pattern signal is to be registered. During the Test pattern writing cycle becomes that of the waveform generator WF output test pattern signal to the memory under test MUT1, MUT2 and MUT3 respectively over the associated Driver circuit groups DR created and written in a memory cell, the by the address signal has designated address.

During one Test pattern read cycle in which the memory in the test written test pattern signal is read out of it, the Memory offset by the control signal in the reading state. The address signal in this case denotes the memory cell from which the written in this Test pattern signal is read.

During the test pattern read cycle, an expected value pattern is generated by the pattern generator PG and applied to the logical comparator LC. At the same time, a comparison timing signal ST is generated by the timing generator TG generated and applied to the logical comparator LC. On the other hand, a read signal and an address signal from the waveform generator WF are applied to the memories MUT1, MUT2, and MUT3 via the driver circuit group DR, and the memory cell written in the address signal is read out from the memory cell having the address designated by the address signal.

All from the memories MUT1, MUT2 and MUT3 respectively read test pattern signals (Response signals) are each in the associated comparator group of Level comparator groups LVC with one of a not shown Comparison reference voltage source provided reference voltage compared, to see if the test pattern signals each one vorbe vorbe have logical level (potential logical H (high logical Level) or potential logical L (low logic level)). One Response signal whose predetermined logic level has been detected becomes the associated one logical comparator LC passed the response signal with a Expected value pattern supplied from the pattern generator PG (Data) EXP at the time of the comparison timing signal ST which is supplied from the timing generator TG.

If in each case from the memories MUT1, MUT2 and MUT3 read response signals not with that of the pattern generator PG supplied Expectation pattern EXP match, is through the associated logical comparator LC decided that the memory cell of the memory under test, from which the wrong response signal has been read, is faulty, and an error signal indicating this condition generated. Usually This error signal is expressed by a signal logical "1" and in a fault analysis memory (not shown).

If on the other hand, the respective response signals equal the expected value pattern EXP, the associated logical comparator LC decides that Memory cell of the memory under test, from which the response signal has been read, operates normally, and generates a pass signal (usually this "pass" signal is passed through Signal is expressed logically "0"). This "pass" signal will become common not stored in the error analysis memory.

If the test is completed, the in the error analysis memory stored error signals read out of this to recognize whether the memory under test is normal or faulty.

In In recent years, the demand for each with high Speed operable semiconductor memory increasingly increased. to Fulfillment of this Demand semiconductor memories have been proposed, each have an isochronous interface, and as memory of the synchronous type or synchronous memory. Here, with a synchronous memory is a memory of a type in which, if a clock and the one or more most significant Bits of an address signal from the outside be applied to the memory in the memory internally the or the least significant bits of the address signal having address signal is generated synchronously with the clock, and to every address in the Memory by the one or least significant bits corresponding address signal accessed at high speed. The result is that a reading and writing at high speed possible.

at This type of synchronous storage is at each memory The output side adds the function of outputting a clock, the the synchronization of out of memory during a data read cycle data being read out (the clock output function is in the memory provided integrally). If this type of storage is actually in a product is incorporated and used, a method is used in which the timing of the data read from the memory a new time setting using the added output function output clock and then the waveform of the clock new shaped data is formed.

The reason for this will now be explained. When a high-speed operation is performed, the period of time during which the waveform of the data read from the memory is fixed or fixed is extremely short. Further, since the response rates of the memory elements differ from each other due to nonuniformities or deviations during the manufacturing process or the like, the phase position of data read out from one memory may be different than the phase position of data read from another memory even if the memories are shared by one or more of them Clock signals are operated, each having the same phase. Therefore, it is difficult to clock the data read from the respective memories by an externally generated clock. For this reason, the drive clock in this type of memory is routed inside each memory so that it is executed internally in each memory and data is read out from each memory in synchronization with this clock. At the same time, the clock is output from each memory. The read-out data is thus output from each memory at the same timing as the clock. In addition, the clock externally timing the data read from each memory using the clock output from the clock output function of each memory.

at simultaneously testing a plurality of such synchronous ones Saving occurs at the timing output stage (phase) of these Store read test pattern signals (data) a nonuniformity due to the unevenness in the production of the respective memory or the like, such as mentioned above. In addition, can also the phase angle of the clock output function of each memory output clocks irregularities demonstrate.

4 shows a timing chart for explaining the operation of in 3 shown memory MUT1, MUT2 and MUT3 in their simultaneous test by the in 3 The memory test apparatus shown in FIG. 1, wherein the memories are the synchronous memories explained above, and each memory has nonuniformity in the manufacturing method or the like.

4A shows an input clock CLK0 applied to each of the memories MUT1, MUT2 and MUT3 while in 4B internal clocks CLK1, CLK2 and CLK3 passing through the respective memories MUT1, MUT2 and MUT3 and output to the outside, respectively. At the in 4B In the example shown, a state is shown in which the internal clock CLK2 output from the memory MUT2 is slightly delayed from the input clock CLK0, whereas the input clocks CLK1 and CLK3 respectively output from the memories MUT1 and MUT3 are greatly delayed from the input clock CLK0 (in accordance with FIG In the drawing, the input clock CLK1 is delayed by φ1 from the internal clock CLK2, while the internal clock CLK3 is further delayed from the internal clock CLK1 by φ1).

The data read out of the memories MUT1, MUT2 and MUT3, respectively D1, D2 and D3 differ in their mutual phase position each strong, which is due to the nonuniformity of the manufacturing process or the like. However, since the read data D1, D2 and D3 from the memories in synchronization with the internal clocks CLK1, CLK2 and CLK3 are read out, therefore, those from the memory MUT1 read data by φ1 compared to the memory MUT2 data D2 delayed, and the data D3 read from the memory MUT3 continue to be opposite φ2 the data read from the memory MUT2 under test D2 delayed. As a result, the phase delays the read-out data D1, D2 and D3 are the same as the phase delays the internal clocks CLK1, CLK2 and CLK3.

In other words, the data D2 read from the memory MUT2 is slightly delayed from the input clock CLK0, while the data D1 and D3 read from the memories MUT1 and MUT3 are greatly delayed from the input clock CLK0, respectively. Furthermore, in 4C a command for switching from a test pattern writing cycle to a test pattern reading cycle or from a test pattern reading cycle to a test pattern writing cycle is illustrated in the illustrated example of the case where a read command is supplied to execute a test pattern read cycle.

As mentioned above, the data (test pattern signals) stored in the memories MUT1 and MUT3 are read out with large phase delays due to the non-uniformity or unevenness of the manufacturing process or the like, and also the respective internal clocks CLK1 and CLK3 which are output simultaneously have large phase delays , On the other hand, the in 4E shown, to be applied to all logical comparator LC from the timing generator TG comparison timing signal ST based on the input clock CLK0 generated as reference timing. Therefore, the comparison timing signal ST is unaffected by the phase delay of the data read from the memory under test. The comparison timing signal ST may therefore be a suitable clock signal for the read-out, almost no phase delay data D2, but is not a correct clock signal for at least the readout data D3 having the largest phase delay. Therefore, if semiconductor memories provided with large variations in the delay time are mixed, the disadvantage arises that the conventional semiconductor memory tester can not test multiple memories at the same time.

It An object of the present invention is to provide a semiconductor memory test apparatus which a logical comparison process with a correct timing To run can, even if the phases of internal, from a plurality of simultaneously each of the semiconductor memories outputted clocks are non-uniform.

The The above object is achieved with a semiconductor memory test device according to the claim 1 or a semiconductor memory test method according to the claim 3 solved. An advantageous development of the invention is the subject of Claim 2.

at the structure of the invention will be the phase of out of a majority of in the test, data to be tested simultaneously to be tested before starting of the test and it becomes one of each measured phase corresponding delay time in the associated delay circuit set in the signal path of the comparison timing signal is provided. Therefore, even if the phases of off a plurality of memories to be tested simultaneously Data are mutually uneven, a comparison time control signal with one for each phase in the test correct phase to the appropriate be created logical comparator. As a result, the Memory can be tested at the same time, even if those in the test Memory have a very short setting period for the read-out data, and a significant phase difference between the time locations the read out data is present, as with high-speed memories the case is.

With the semiconductor memory test method according to claim 3 provided a method including the phases of the comparison timing signals even if internal, from a plurality of simultaneously too testing clocks issued non-uniform phase shifts can correct, according to this non-uniformity, so that one correct logical comparison is performed.

SHORT DESCRIPTION THE DRAWINGS

1 shows a block diagram of an embodiment of a semiconductor memory test device according to the invention;

2 shows a timing diagram for explaining the operation of the in 1 illustrated semiconductor memory tester;

3 Fig. 16 is a block diagram illustrating an example of a conventional semiconductor memory test apparatus;

4 shows a timing diagram for explaining the operation of the in 3 illustrated semiconductor memory tester; and

5 FIG. 12 is a waveform diagram for explaining an embodiment of a method of measuring the phase of a clock output from a memory under test. FIG.

DETAILED DESCRIPTION OF EXAMPLES

Hereinafter, a preferred embodiment of the present invention with reference to the 1 and 2 described in detail. Here are the sections and elements according to 1 that the in 3 shown sections and elements correspond, provided with the same reference numerals and will only be described as necessary again.

1 shows a block diagram of an embodiment of a ertindungsgemäßen semiconductor memory test device. This semiconductor memory tester is similar to the conventional one in FIG 3 Also, the semiconductor memory test apparatus shown in FIG. 1 includes a pattern generator PG, a timing generator TG, a waveform generator WF, a driver circuit group DR, a level comparator group LVC, and a plurality of logic comparators LC.

In the present invention, the semiconductor memory test apparatus is constructed such that variable delay circuits DY1, DY2, and DY3 having a number corresponding to the number of memories MUT1, MUT2, and MUT3 in the test are arranged in the supply path of a comparison timing signal ST during a test pattern read cycle of the timing generator TG is applied to all the logic comparators LC, and the phase of the comparison timing signal ST becomes the same as the phase of the corresponding data read from the memories under test. At the in 1 example shown is similar to that in 3 As shown in the conventional semiconductor memory tester, the number of memories to be tested simultaneously is set to three. Therefore, the driver circuit group TR is formed by three driver groups, and also the level comparator group LVC is made up of three comparator groups. Furthermore, three logical comparators LC are provided. In addition, there are three variable delay circuits. Of course, however, the number of these elements may be changed depending on the number of memories to be tested simultaneously. The number of memories to be tested simultaneously is arbitrary and may include, for example, many memories such as 32 memories or 64 memories.

In this embodiment, a phase meter PC for measuring the phases of clocks output from test memory MUT1, MUT2, and MUT3 before starting the test of these memories, and setting delay times of associated variable ones Delay circuits DY1, DY2 and DY3 provided depending on the measurement result.

In front the beginning of the test of the memory under test thus becomes a clock is fed into the memories MUT1, MUT2 and MUT3 to be tested and it will be the Phasenverzögerun conditions the clocks issued by these memories to be tested by the phase meter PC measured. The phase measuring device PC provides delay times of corresponding variable delay circuits DY1, DY2 or DY3 according to the respective magnitudes of the phase delays one. This setting of the delay times the variable delay circuits DY1, DY2 and DY3 will be executed once each time before the test starts the memories to be tested are exchanged, and they become these Set values of the variable delay circuits DY1, DY2 and DY3 unchanged After the beginning of the test, keep it until the test of this Memory to be tested is completed.

by virtue of This procedure is used in the test pattern reading cycle after the Start of the test, in which the memories MUT1 to be tested in the MUT2 and MUT3 stored data are read from these that from the timing generator TG to the variable delay circuits DY1, DY2 and DY3 supplied comparison timing signals ST to the corresponding logical comparators LC passed after they in the respective delay circuits set delay times delayed are. Since these comparison timing signals ST thus by time periods delayed be the phase delays the data read from the corresponding memories to be tested and then to the corresponding logical comparators LC can be routed out the data to be tested read with the data from the pattern generator PG supplied expected value pattern EXP can be compared logically correct.

The operation of the memory test apparatus constructed in the above-mentioned manner will be described with reference to FIG 2 illustrated timing diagram described in detail.

2A shows an input clock CLK0 applied to all the memories MUT1, MUT2 and MUT3 to be tested. 2 B FIG. 12 shows internal clocks CLK1, CLK2 and CLK3 which pass internally through the respective memories MUT1, MUT2 and MUT3 to be tested and in synchronism with the read-out ones in FIG 2D shown data D1, D2 and D3 are output. In the example according to 2 B the internal clock CLK2 output from the memory under test MUT2 is in a state slightly delayed from the input clock CLK0, whereas the internal clock CLK1 read from the memory MUT1 to be tested is delayed from the internal clock CLK2 by φ1 and that from the one to be tested Memory MUT3 output internal clock CLK3 against the input clock CLK1 is further delayed by φ2.

Even if the same input clock CLK0 enters the memory MUT1 to be tested, MUT2 and MUT3 is entered, when this clock passes through each memory to be tested passes internally and is output, a phase delay at each of the internal memories to be tested MUT1, MUT2 and MUT3 output clocks according to the distribution the internal delay times each memory to be tested due to the spread of the manufacturing process or similar attributable Differences between the internal delay times of the test to be tested Memory up.

2D shows the data D1, D2 and D3 respectively read from the memories MUT1, MUT2 and MUT3 to be tested during the test pattern read cycle. With respect to these read-out data D1, D2 and D3, due to differences in the internal delay times of the memories to be tested, phase differences occur between the read-out data D1, D2 and D3 due to the nonuniformities of the manufacturing process or the like. In addition, the readout data D1, D2 and D3 are outputted from the memories in synchronization with the respective internal clocks CLK1, CLK2 and CLK3 so that the read-out data D1 output from the memory MUT1 to be tested is outputted from the memory MUT2 to be tested. data D2 read out are delayed by φ1, while the data D3 outputted from the memory MUT3 to be tested is further delayed by φ2 from the read-out data D1 output from the memory MUT1 to be tested. That is, the read-out data D1 and the internal clock CLK1, the read-out data D2 and the internal clock CLK2 and the read-out data D3 and the internal clock CLK3 are respectively output at the same phase.

2E FIG. 12 shows a comparison timing signal ST output from the timing generator TG, which is applied to the variable delay circuits DY1, DY2, and DY3. If this comparison timing signal ST were applied to all logic comparators LC with its unchanged phase, it would be understandable that at least the logical comparison of the read-out data D3 could be performed at the in 2D shown state of the read data are not normally performed.

2F FIG. 12 shows waveforms of the clocks CLK1-1, CLK2-2 and CLK3-3 respectively output from the memories to be tested when the same clock is input to the memories MUT1, MUT2 and MUT3 to be tested. In this embodiment, these output clocks CLK1-1, CLK2-2 and CLK3-3 are input to the phase meter CP, which measures the mutual phase differences between the clocks CLK1-1, CLK2-2 and CLK3-3. Since the number of memories to be tested is three in this embodiment, the phase of that clock is used as the reference phase, and the average one of the three clocks CLK1-1, CLK2-2 and CLK3-3 output from the respective memories to be tested has an average phase delay value has. When the phase of the one clock having the average phase delay value among the three clocks CLK1-1, CLK2-2 and CLK3-3 is used as the reference phase, there is obtained the advantage that the time width of each of the variable delay circuits DY1, DY2 and DY3 delay times to be set can be narrowed.

At the in 2F In the example shown, the phase of the clock CLK1-1 is set as the reference phase, since this clock CLK1-1 output from the memory MUT1 under test lies in a middle position between the two remaining clocks. Thus, the clock CLK2-2 output from the memory under test MUT2 can be detected as a clock having a phase leading by φ1 from the reference phase, for example. Further, the clock CLK3-3 output from the memory under test MUT3 may be detected as a clock having a phase delayed from the reference phase by, for example, φ2.

The Taktmeßeinrichtung CP represents in the variable delay circuit associated with the clock CLK1-1 DY1 based on the detected phase difference a delay value τ0 (for example is a delay size of 10 ns as τ0 determined). The clock measuring device CP represents in the variable delay circuit associated with the clock CLK2-2 DY2 a delay value -τ1 corresponding to the leading phase φ1 (a smaller value than 10 ns). The phase meter CP continues to provide in the CLK3-3 associated with the clock variable delay circuit DY3 one of the delayed Phase φ2 corresponding delay value + τ2 on (a greater value than 10 ns).

Thus, due to the adjustment of the delay times in all the variable delay circuits DY1, DY2 and DY3 as shown in FIG 2G a comparison timing signal S1 passed through the variable delay circuit DY1 is delayed by a delay time corresponding to the delay value τ0 and applied to the associated logical comparator LC. Likewise, a comparison timing signal S2 passed through the variable delay circuit DY2 is delayed by a delay time corresponding to the delay value -τ1 and applied to the associated logic comparator LC. Further, a comparison timing signal S3 passed through the variable delay circuit DY3 is delayed by a delay time corresponding to the delay value + τ2 and applied to the corresponding logic comparator LC. That is, the comparison timing signal S2 is given a phase difference of -τ1 with respect to the comparison timing signal S1, and the phase comparison signal S3 is impressed with a phase difference of + τ2 with respect to the comparison timing signal S1.

As with reference to the in 2D shown read data D1, D2 and D3 and the in 2G Thus, the timing of the comparison timing signal S1 coincides with that of the read-out data D1 while the timing of the comparison timing signal S2 coincides with that of the read-out data D2, and the timing of the comparison timing signal S3 with that of the read-out data D3 matches. Thus, even if semiconductor memories having large deviations of the delay times are present in mixed form, the data D1, D2 and D3 read from the respective associated memories MUT1, MUT2 and MUT3 to be tested in the respective logic comparators LC on the basis of these comparison timing signals S1, S2 or S3 are temporally logically compared with the expected value pattern supplied by the pattern generator PG.

5 FIG. 12 is a waveform diagram for explaining an example of a method of measuring the phase of a clock output from each of the memories to be tested before the test. FIG. 5A shows the waveform of a clock CLK output from a memory under test. In this example, the comparison timing pulse becomes close to the boundary between the logical H range ("pass" range) and the logical L (error range) range of the clock CLK as shown in FIG 5B and 5F shifted, for example, from the range logical H → range logical L → range logical H → range logical L ..., such that the comparison timing pulse approaches the limit in the sequential order, so that a boundary point between the logical H and the logical L range is determined. Subsequently, the time span from the time at which the Clock CLK is set to the limit point as the measured value for the phase φM of this clock. Of course, the phase of the clock output from the memory under test may also be measured using other measurement techniques.

at the above-explained embodiment becomes the phase of the clock output from the memory under test measured before the start of the test. However, it is difficult to measure the phase of the data read, since the read out Data have a period of logic L. However, at the Measurement of the phase of the data read out to set the delay time the variable delay circuit the Correction of the comparison timing signal not timely executed because the data is read at high speed. Therefore before the start of the test, the same clock will be tested in each of the ones to be tested Memory is fed in and the phase of the clock is measured, the almost output with the same phase as the read data becomes.

Out From the foregoing description, it can be seen that the present invention has the great advantage is achieved that several Semiconductor memory can be tested simultaneously even if the length of time the waveform has a fixed value, due to the high speed change of the waveform of the read data is extremely short, as with a synchronous Memory is the case, with a difference between the times the output of the read-out data is present.

Claims (3)

Semiconductor memory tester with a pattern generator (PG) for outputting pattern data for generating a test pattern signal, an address signal and a control signal to be stored in a plurality of semiconductor memories to be tested and an expected value pattern (EXP), each of which the semiconductor memory is a synchronous semiconductor memory, the a clock for re-timing the output timing of the output data read from the respective semiconductor memory can a waveform generator (WF) for conversion the pattern data output from the pattern generator (PG) into the Test pattern signal, the address signal and the control signal, each having a real waveform; one logical comparator (LC) to compare each one the data to be tested semiconductor memory read data with that of expected value pattern (EXP) for the determination, which is output to the pattern generator, whether the respective semiconductor memory under test is faulty is or is not, a phase measuring device (CP) for measuring the phase of one of each of the plurality of semiconductor memories to be tested output clock before the start of the test of the semiconductor memory to be tested; and a plurality of variable delay circuits (DY1, DY2, DY3), in each of which a delay time in accordance with the phase measured by the phase measuring device is adjustable, such that each variable delay circuit is applied to it Comparison timing signal (ST) by the delay time set in it delayed and that delayed Comparison timing signal (S1, S2, S3) to the associated logical Comparator applies. A semiconductor memory test apparatus according to claim 1, wherein the phase measuring device is designed to be the phase of each of the ones to be tested Semiconductor memory output clocks measured by before at the beginning of the test, to test the same clock in the majority of Enters semiconductor memories; and in the semiconductor memories respectively associated variable delay circuits delay times to adjust according to the measured phases; thereby the phases that of the variable delay circuits output comparison timing signals in each case with the phases the data read from the associated semiconductor memories to be tested to match and the number of logical comparators provided is the same is great like the number of variable delay circuits, each one logical comparator read from the respective associated semiconductor memory Data with the expectation pattern output from the pattern generator at the time location of the associated variable delay circuit supplied Logically compares the comparison timing signal. A semiconductor memory test method, comprising the steps of: converting pattern data output from pattern generating means into a test pattern signal, an address signal, and a control signal, each having a real waveform; Supplying the test pattern signal, the address signal and the control signal to each semiconductor memory to be tested for writing the test pattern signal into the semiconductor memories to be tested, wherein each of the semiconductor memories is a synchronous semiconductor memory, wherein a clock for re-timing the output timing of read-out from the respective memory Data is output; Reading the written test pattern signal from each of the semiconductor memories; and logical comparison of the read Testmus an expected value pattern at a timing of a comparison timing signal generated by a timing generation means to determine whether or not the semiconductor memory under test is faulty, the semiconductor memory test method comprising the further steps of: inputting the same clock to the plurality of semiconductor memories to be tested and measuring the phase of a clock output from each of the semiconductor memories to be tested before starting a test of the semiconductor memories; Setting delay times corresponding to the measured values of the phases of the clocks output from the semiconductor memories in the semiconductor memories, respectively, associated with comparison timing delay means; and logically comparing data read out from the respective semiconductor memories with the expected value pattern under the timing by a delayed comparison timing signal supplied from the respectively assigned comparison timing delay means.