DE19908446A1 - DRAM-Zellenkondensator und Verfahren zu dessen Herstellung - Google Patents

DRAM-Zellenkondensator und Verfahren zu dessen Herstellung

Info

Publication number
DE19908446A1
DE19908446A1 DE19908446A DE19908446A DE19908446A1 DE 19908446 A1 DE19908446 A1 DE 19908446A1 DE 19908446 A DE19908446 A DE 19908446A DE 19908446 A DE19908446 A DE 19908446A DE 19908446 A1 DE19908446 A1 DE 19908446A1
Authority
DE
Germany
Prior art keywords
layer
conductive
opening
insulation layer
conductive pole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19908446A
Other languages
German (de)
English (en)
Inventor
Byung-Jun Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE19908446A1 publication Critical patent/DE19908446A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE19908446A 1998-04-25 1999-02-26 DRAM-Zellenkondensator und Verfahren zu dessen Herstellung Withdrawn DE19908446A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980014851A KR100270210B1 (ko) 1998-04-25 1998-04-25 디램 셀 커패시터 및 그의 제조 방법

Publications (1)

Publication Number Publication Date
DE19908446A1 true DE19908446A1 (de) 1999-11-04

Family

ID=19536714

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19908446A Withdrawn DE19908446A1 (de) 1998-04-25 1999-02-26 DRAM-Zellenkondensator und Verfahren zu dessen Herstellung

Country Status (7)

Country Link
JP (1) JP2000022099A (fr)
KR (1) KR100270210B1 (fr)
CN (1) CN1236993A (fr)
DE (1) DE19908446A1 (fr)
FR (1) FR2778019A1 (fr)
GB (1) GB2336716B (fr)
TW (1) TW412828B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7119389B2 (en) 2002-07-08 2006-10-10 Samsung Electronics Co., Ltd. Dynamic random access memory cells having laterally offset storage nodes

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426249B1 (en) * 2000-03-16 2002-07-30 International Business Machines Corporation Buried metal dual damascene plate capacitor
KR100510527B1 (ko) 2003-05-01 2005-08-26 삼성전자주식회사 스토리지 전극을 포함하는 반도체 소자 및 그 제조 방법
KR100545865B1 (ko) * 2003-06-25 2006-01-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN111599812B (zh) * 2015-04-30 2023-07-04 联华电子股份有限公司 静态随机存取存储器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438011A (en) * 1995-03-03 1995-08-01 Micron Technology, Inc. Method of forming a capacitor using a photoresist contact sidewall having standing wave ripples
JP2776331B2 (ja) * 1995-09-29 1998-07-16 日本電気株式会社 半導体装置およびその製造方法
US5643819A (en) * 1995-10-30 1997-07-01 Vanguard International Semiconductor Corporation Method of fabricating fork-shaped stacked capacitors for DRAM cells
US5721154A (en) * 1996-06-18 1998-02-24 Vanguard International Semiconductor Method for fabricating a four fin capacitor structure
US5744833A (en) * 1996-08-16 1998-04-28 United Microelectronics Corporation Semiconductor memory device having tree-type capacitor
GB2322964B (en) * 1997-03-07 2001-10-17 United Microelectronics Corp Polysilicon CMP process for high-density DRAM cell structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7119389B2 (en) 2002-07-08 2006-10-10 Samsung Electronics Co., Ltd. Dynamic random access memory cells having laterally offset storage nodes
US7504295B2 (en) 2002-07-08 2009-03-17 Samsung Electronics Co., Ltd. Methods for fabricating dynamic random access memory cells having laterally offset storage nodes
DE10330072B4 (de) * 2002-07-08 2010-07-22 Samsung Electronics Co., Ltd., Suwon Zellen eines dynamischen Speichers mit wahlfreiem Zugriff mit seitlich versetzten Speicherknoten und Verfahren zu ihrer Herstellung

Also Published As

Publication number Publication date
GB9905192D0 (en) 1999-04-28
GB2336716A (en) 1999-10-27
CN1236993A (zh) 1999-12-01
TW412828B (en) 2000-11-21
JP2000022099A (ja) 2000-01-21
GB2336716B (en) 2000-11-15
KR19990081113A (ko) 1999-11-15
FR2778019A1 (fr) 1999-10-29
KR100270210B1 (ko) 2000-10-16

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8139 Disposal/non-payment of the annual fee