DE19800089A1 - Halbleitervorrichtung und Verfahren zu ihrer Herstellung - Google Patents

Halbleitervorrichtung und Verfahren zu ihrer Herstellung

Info

Publication number
DE19800089A1
DE19800089A1 DE19800089A DE19800089A DE19800089A1 DE 19800089 A1 DE19800089 A1 DE 19800089A1 DE 19800089 A DE19800089 A DE 19800089A DE 19800089 A DE19800089 A DE 19800089A DE 19800089 A1 DE19800089 A1 DE 19800089A1
Authority
DE
Germany
Prior art keywords
layer
transistor
oxide layer
nitrogen
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19800089A
Other languages
German (de)
English (en)
Inventor
Shuichi Ueno
Yoshinori Okumura
Shingenobu Maeda
Shigeto Maegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE19800089A1 publication Critical patent/DE19800089A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE19800089A 1997-05-14 1998-01-02 Halbleitervorrichtung und Verfahren zu ihrer Herstellung Withdrawn DE19800089A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12394197A JP3648015B2 (ja) 1997-05-14 1997-05-14 半導体装置

Publications (1)

Publication Number Publication Date
DE19800089A1 true DE19800089A1 (de) 1998-11-19

Family

ID=14873149

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19800089A Withdrawn DE19800089A1 (de) 1997-05-14 1998-01-02 Halbleitervorrichtung und Verfahren zu ihrer Herstellung

Country Status (7)

Country Link
US (1) US5998828A (https=)
JP (1) JP3648015B2 (https=)
KR (1) KR100315740B1 (https=)
CN (1) CN100401527C (https=)
DE (1) DE19800089A1 (https=)
FR (1) FR2763425B1 (https=)
TW (1) TW393768B (https=)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3602679B2 (ja) * 1997-02-26 2004-12-15 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6188101B1 (en) * 1998-01-14 2001-02-13 Advanced Micro Devices, Inc. Flash EPROM cell with reduced short channel effect and method for providing same
JP3769120B2 (ja) * 1998-05-08 2006-04-19 株式会社東芝 半導体素子
US6249841B1 (en) * 1998-12-03 2001-06-19 Ramtron International Corporation Integrated circuit memory device and method incorporating flash and ferroelectric random access memory arrays
JP2001093903A (ja) * 1999-09-24 2001-04-06 Toshiba Corp 半導体装置及びその製造方法
JP3613113B2 (ja) * 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6333244B1 (en) * 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
JP4823408B2 (ja) 2000-06-08 2011-11-24 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
US6956757B2 (en) 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
JP2002208645A (ja) * 2001-01-09 2002-07-26 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
US6747318B1 (en) * 2001-12-13 2004-06-08 Lsi Logic Corporation Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides
US7314812B2 (en) * 2003-08-28 2008-01-01 Micron Technology, Inc. Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal
JP2005101466A (ja) * 2003-09-26 2005-04-14 Renesas Technology Corp 半導体記憶装置
JP4513497B2 (ja) * 2004-10-19 2010-07-28 ソニー株式会社 固体撮像装置
US7488635B2 (en) * 2005-10-26 2009-02-10 Freescale Semiconductor, Inc. Semiconductor structure with reduced gate doping and methods for forming thereof
KR100742758B1 (ko) * 2005-11-02 2007-07-26 경북대학교 산학협력단 플래시 메모리 소자 및 그 제조방법
JP5567247B2 (ja) * 2006-02-07 2014-08-06 セイコーインスツル株式会社 半導体装置およびその製造方法
US7573095B2 (en) * 2006-12-05 2009-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cells with improved program/erase windows
US8217435B2 (en) 2006-12-22 2012-07-10 Intel Corporation Floating body memory cell having gates favoring different conductivity type regions
US7652923B2 (en) * 2007-02-02 2010-01-26 Macronix International Co., Ltd. Semiconductor device and memory and method of operating thereof
WO2009061834A1 (en) * 2007-11-05 2009-05-14 Contour Semiconductor, Inc. Low-cost, high-density rectifier matrix memory
US8969969B2 (en) * 2009-03-20 2015-03-03 International Business Machines Corporation High threshold voltage NMOS transistors for low power IC technology
JP2012028790A (ja) * 2011-08-19 2012-02-09 Renesas Electronics Corp 半導体装置
CN103107076B (zh) * 2011-11-11 2015-04-29 中芯国际集成电路制造(上海)有限公司 分离栅极式快闪存储器及存储器组的制作方法
CN103377901A (zh) * 2012-04-28 2013-10-30 无锡华润上华科技有限公司 多晶硅栅极的形成方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774197A (en) * 1986-06-17 1988-09-27 Advanced Micro Devices, Inc. Method of improving silicon dioxide
JPH04157766A (ja) * 1990-10-20 1992-05-29 Sony Corp シリコンゲートｐチャンネルＭＯＳ半導体装置の製造方法
JP3830541B2 (ja) * 1993-09-02 2006-10-04 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US5514902A (en) * 1993-09-16 1996-05-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having MOS transistor
JPH07335883A (ja) * 1994-06-15 1995-12-22 Toshiba Corp 半導体装置の製造方法
JPH08139315A (ja) * 1994-11-09 1996-05-31 Mitsubishi Electric Corp Ｍｏｓトランジスタ、半導体装置及びそれらの製造方法
US5674788A (en) * 1995-06-06 1997-10-07 Advanced Micro Devices, Inc. Method of forming high pressure silicon oxynitride gate dielectrics
US5567638A (en) * 1995-06-14 1996-10-22 National Science Council Method for suppressing boron penetration in PMOS with nitridized polysilicon gate
JPH0922999A (ja) * 1995-07-07 1997-01-21 Seiko Epson Corp Ｍｉｓ型半導体装置及びその製造方法
US5734186A (en) * 1996-09-16 1998-03-31 Delco Electronics Corporation CMOS voltage clamp

Also Published As

Publication number Publication date
US5998828A (en) 1999-12-07
KR100315740B1 (ko) 2002-05-30
CN100401527C (zh) 2008-07-09
TW393768B (en) 2000-06-11
JPH10313098A (ja) 1998-11-24
FR2763425B1 (fr) 2002-01-04
JP3648015B2 (ja) 2005-05-18
FR2763425A1 (fr) 1998-11-20
CN1199248A (zh) 1998-11-18
KR19980086383A (ko) 1998-12-05

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OP8 Request for examination as to paragraph 44 patent law
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