DE1966236A1 - Verfahren zum Einbringen von Stoerstellen in Halbleiterstrukturen - Google Patents

Verfahren zum Einbringen von Stoerstellen in Halbleiterstrukturen

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Publication number
DE1966236A1
DE1966236A1 DE19691966236 DE1966236A DE1966236A1 DE 1966236 A1 DE1966236 A1 DE 1966236A1 DE 19691966236 DE19691966236 DE 19691966236 DE 1966236 A DE1966236 A DE 1966236A DE 1966236 A1 DE1966236 A1 DE 1966236A1
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Germany
Prior art keywords
impurities
semiconductor
semiconductor structures
gold
interference points
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Granted
Application number
DE19691966236
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English (en)
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DE1966236B2 (de
DE1966236C3 (de
Inventor
Schumann Jun Paul August
Duffy Michael Charles
Tsu-Hsing Yeh
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International Business Machines Corp
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International Business Machines Corp
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Publication of DE1966236A1 publication Critical patent/DE1966236A1/de
Publication of DE1966236B2 publication Critical patent/DE1966236B2/de
Application granted granted Critical
Publication of DE1966236C3 publication Critical patent/DE1966236C3/de
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/062—Gold diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/904—Charge carrier lifetime control

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Physical Vapour Deposition (AREA)
  • Element Separation (AREA)
  • Thyristors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

Verfahren zum Einbringen von Störstellen in Halbleiter strukturen
Die Erfindung betrifft ein Verfahren zum selektiven Einbringen von die Lebensdauer von Ladungsträgern beeinflussenden Störstellen (Haftstellen) in dotierte Halbleiterstrukturen.
Es ist bekannt, Halbleiterbauelemente mit Störstellen zu dotieren, welche Haftstellen für Ladungsträger innerhalb des Kristalls bilden. Für derartige Störstellen wird besonders Gold verwendet. Um die Lebensdauer der Ladungsträger zu reduzieren, werden derartige Haftstellen im Kristallgitter eingebaut, wodurch die Lebensdauer der Ladungsträger verringert wird. Werden daher solche Haftstellen in das Gebiet des Basis-Kollektor-Überganges eines Transistors gebracht, so erhält man kürzere Schaltzeiten für diesen Transistor. Es hat sich jedoch herausgestellt, daß beim Eindiffundieren von derartigen Störstellen besondere Kanäle auftreten, die zwischen Regionen gleichen Leitfähigkeitstyps, wie z. B. zwischen dem diffundierten Emitter und der Kollektorzone eines Transistors gebildet werden, wodurch ein gewisser • Kurzschluß zwischen diesen zwei Regionen auftritt und die Wirkungsweise der T ran sis tor struktur ernsthaft beeinträchtigt wird. Derartige Kanäle sind also ein Struktur effekt innerhalb der Basiszone, wodurch elektrische Kurzschlüsse während des Betriebes der Vorrichtung möglich sind und welche zurückgeführt werden auf Wechselwirkungen der die Leitfähigkeit bestimmenden .Dotierungsmaterialien, beispielsweise des Phosphors oder Bors mit dem Gold während des Diffusionsprozesses. Die Haftstellen, wie Gold, werden nur benö-
10 9 8 51/U19
tigt im Basis-Kollektor-PN-Übergang eines Transistors. Es ist jedoch gegenwärtig mit Hilfe der Festkörperdiffusion noch nicht möglich, Gold nur an diesen PN-Übergängen im Halbleiterkörper einzubauen. Vielmehr entsteht eine Golddotierung im gesamten Halbleiterkristall, was darauf zurückzuführen ist, daß das Gold einen sehr großen Diffusionskoeffizienten bei den verschiedensten Diffusioitfemperaturen im Halbleiter besitzt.
Insbesondere bei der Herstellung integrierter Schaltungen mit hoher Schaltungsdichte wird die Ausbeute an guten Halbleitervorrichtungen durch die oben beschriebenen Kanalbildungen beeinflußt. Es wird nicht nur das einzelne Halbleiterbauelement durch die Entstehung eines Kanals beeinträchtigt oder zerstört, sondern die gesamte monolithische Struktur kann durch das Ausfallen eines Elementes unwirksam werden.
Es ist daher die Aufgabe der vorliegenden Erfindung, eine Halbleiter struktur herzustellen, die nur in begrenzten Gebieten Störstellen zur Verringerung der Lebensdauer von Ladungsträgern aufweisen und die keine durch die Störstellen bedingten, kurzschließenden Kanäle enthalten. Diese Aufgabe wird bei dem anfangs genannten Verfahren erfindungsgemäß dadurch vermieden, daß das Einbringen der Störstellen durch Bombardement der Halbleiter struktur mit Ionen definierter Masse und Energie erfolgt. Vorteilhaft werden die Störstellen in das Gebiet des Basis-Kollektor-Überganges eines Transistors eingebracht. Das Bombardement der Halbleiterstruktur erfolgt vorzugsweise mit Goldatomen.
Das Einbringen von Dotierungsstoffen in Halbleiter durch Ionenimplantation ist an sich bekannt. Diese Maßnahme wurde aber bisher nur zur Änderung der Leitfähigkeit des Halbleitermaterials, nicht jedoch zur Beeinflussung der Lebensdauer von Ladungsträgern in ausgewählten dotierten Gebieten durchgeführt.
Docket FI 967 056 A 109851/1419
Mit Hilfe des Ionenimplantationsverfahrens ist es möglich, Gddverunreinigungen nur in die Kollektorübergänge einzubauen, wodurch nur hier die Lebensdauer der Minoritätsladungsträger reduziert und auf diese Weise eine Verkürzung der Schaltzeit erreicht wird. Weiterhin verhindert diese Ionenimplantation die Wechselwirkung zwischen Phosphor- oder Bor-Verunreinigungen in der Basiszone mit den eingebauten Goldstör stellen, da das Gold nur
die in den Kollektorübergängen vorhanden ist. Wenn auch/die Leitfähigkeit der Halbleiterzonen bestimmenden Dotierungsmaterialien durch Ionenimplantation eingebracht sind, d. h. die gesamte integrierte Schaltung bei niedrigen Temperaturen hergestellt wid, dann erreicht die Halbleiter struktur niemals eine ä so hohe Temperatur, daß das implantierte Gold ausdiffundiert und in die Basiszone gerät. Beispielsweise ist es möglich, eine mit Gold dotierte Region mit einer Weite von etwa Iu jenseits des Kollektor-Basisüberganges mit Hilfe der Ionenimplantation herzustellen. Bei Verwendung von hohen Temperaturen während des Herstellungsprozesses der Halbleiter struktur dagegen ist es nur notwendig, daß derartige Haftstellen nach dem letzten Hochtemperatur-Verfahrensschritt eingebaut werden.
109851/U19
FI 967 056 4

Claims (3)

PATENTANSPRÜCHE
1. J \rerfahren zum selektiven Einbringen von die Lebensdauer von Ladungsträgern beeinflussenden Störstellen (Haftstellen) in dotierte Halbleiterstrukturen, dadurch gekennzeichnet, daß das Einbringen der Störstellen durch Bombardement der Halbleiter struktur mit Ionen definierter Masse und Energie erfolgt.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Störstellen in das Gebiet des Basis-Kollektor-Überganges eines Transistors eingebracht werden.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß das Bombardement der Halbleiter struktur mit Goldatomen erfolgt.
109851 / U19
DE1966236A 1968-08-06 1969-07-29 Verfahren zum Einbringen von Haftstellen in Transistorhalbleiterstrukturen Expired DE1966236C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US75065068A 1968-08-06 1968-08-06

Publications (3)

Publication Number Publication Date
DE1966236A1 true DE1966236A1 (de) 1971-12-16
DE1966236B2 DE1966236B2 (de) 1975-08-07
DE1966236C3 DE1966236C3 (de) 1979-07-19

Family

ID=25018702

Family Applications (3)

Application Number Title Priority Date Filing Date
DE1966237A Expired DE1966237C3 (de) 1968-08-06 1969-07-29 Verfahren zur Erhöhung des Gradienten von elektrisch aktiven Störstellenkonzentrationen
DE1966236A Expired DE1966236C3 (de) 1968-08-06 1969-07-29 Verfahren zum Einbringen von Haftstellen in Transistorhalbleiterstrukturen
DE19691938365 Pending DE1938365B2 (de) 1968-08-06 1969-07-29 Verfahren zum herstellen eines transistors

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Application Number Title Priority Date Filing Date
DE1966237A Expired DE1966237C3 (de) 1968-08-06 1969-07-29 Verfahren zur Erhöhung des Gradienten von elektrisch aktiven Störstellenkonzentrationen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE19691938365 Pending DE1938365B2 (de) 1968-08-06 1969-07-29 Verfahren zum herstellen eines transistors

Country Status (6)

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US (1) US3655457A (de)
JP (3) JPS501636B1 (de)
CA (1) CA922024A (de)
DE (3) DE1966237C3 (de)
FR (1) FR2015121A1 (de)
GB (3) GB1270170A (de)

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Publication number Priority date Publication date Assignee Title
FR2406301A1 (fr) * 1977-10-17 1979-05-11 Silicium Semiconducteur Ssc Procede de fabrication de dispositifs semi-conducteurs rapides
EP0834909A2 (de) * 1989-09-28 1998-04-08 Siemens Aktiengesellschaft Verfahren zur Erhöhung der Spannungsfestigkeit eines mehrschichtigen Halbleiterbauelements

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DE2235865A1 (de) * 1972-07-21 1974-01-31 Licentia Gmbh Halbleiteranordnung aus einer vielzahl von in einem gemeinsamen halbleiterkoerper untergebrachten halbleiterbauelementen
CH560463A5 (de) * 1972-09-26 1975-03-27 Siemens Ag
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JPS5029186A (de) * 1973-07-17 1975-03-25
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DE2341311C3 (de) * 1973-08-16 1981-07-09 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Einstellen der Lebensdauer von Ladungsträgern in Halbleiterkörpern
FR2249491B1 (de) * 1973-10-30 1976-10-01 Thomson Csf
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DE1966236B2 (de) 1975-08-07
DE1938365B2 (de) 1972-12-21
FR2015121A1 (de) 1970-04-24
DE1966237A1 (de) 1972-01-13
DE1966237B2 (de) 1975-07-17
GB1274725A (en) 1972-05-17
JPS5125713B1 (de) 1976-08-02
GB1262705A (en) 1972-02-02
US3655457A (en) 1972-04-11
CA922024A (en) 1973-02-27
DE1938365A1 (de) 1970-02-12
DE1966237C3 (de) 1979-07-12
DE1966236C3 (de) 1979-07-19
GB1270170A (en) 1972-04-12
JPS501636B1 (de) 1975-01-20
JPS528673B1 (de) 1977-03-10

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