DE69120857T2 - Verfahren zum Herstellen eines Siliziumkörpers mit einer daran grenzenden höher dotierten n-leitenden Basisschicht - Google Patents

Verfahren zum Herstellen eines Siliziumkörpers mit einer daran grenzenden höher dotierten n-leitenden Basisschicht

Info

Publication number
DE69120857T2
DE69120857T2 DE69120857T DE69120857T DE69120857T2 DE 69120857 T2 DE69120857 T2 DE 69120857T2 DE 69120857 T DE69120857 T DE 69120857T DE 69120857 T DE69120857 T DE 69120857T DE 69120857 T2 DE69120857 T2 DE 69120857T2
Authority
DE
Germany
Prior art keywords
producing
base layer
type base
silicon body
layer adjoining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69120857T
Other languages
English (en)
Other versions
DE69120857D1 (de
Inventor
Franciscus Petrus Widdershoven
Jan Haisma
Kock Arie Jan Rudolf De
Gorkum Aart Adrianus Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of DE69120857D1 publication Critical patent/DE69120857D1/de
Application granted granted Critical
Publication of DE69120857T2 publication Critical patent/DE69120857T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Thyristors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69120857T 1990-04-24 1991-04-19 Verfahren zum Herstellen eines Siliziumkörpers mit einer daran grenzenden höher dotierten n-leitenden Basisschicht Expired - Fee Related DE69120857T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL9000972A NL9000972A (nl) 1990-04-24 1990-04-24 Werkwijze voor het vervaardigen van een silicium lichaam met een n-type toplaag en een daaraan grenzende, hoger gedoteerde n-type basislaag.

Publications (2)

Publication Number Publication Date
DE69120857D1 DE69120857D1 (de) 1996-08-22
DE69120857T2 true DE69120857T2 (de) 1997-01-30

Family

ID=19856991

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120857T Expired - Fee Related DE69120857T2 (de) 1990-04-24 1991-04-19 Verfahren zum Herstellen eines Siliziumkörpers mit einer daran grenzenden höher dotierten n-leitenden Basisschicht

Country Status (6)

Country Link
US (1) US5688714A (de)
EP (1) EP0454236B1 (de)
JP (1) JP3073257B2 (de)
KR (1) KR100201744B1 (de)
DE (1) DE69120857T2 (de)
NL (1) NL9000972A (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5897362A (en) * 1998-04-17 1999-04-27 Lucent Technologies Inc. Bonding silicon wafers
US20010042866A1 (en) * 1999-02-05 2001-11-22 Carrie Carter Coman Inxalygazn optical emitters fabricated via substrate removal
US6491752B1 (en) * 1999-07-16 2002-12-10 Sumco Oregon Corporation Enhanced n-type silicon material for epitaxial wafer substrate and method of making same
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1312510A (en) * 1969-06-27 1973-04-04 Hitachi Ltd Method of manufacturing a multi-layer semiconductor device
US3879230A (en) * 1970-02-07 1975-04-22 Tokyo Shibaura Electric Co Semiconductor device diffusion source containing as impurities AS and P or B
EP0161740B1 (de) * 1984-05-09 1991-06-12 Kabushiki Kaisha Toshiba Verfahren zur Herstellung eines Halbleitersubstrates
JPH0671043B2 (ja) * 1984-08-31 1994-09-07 株式会社東芝 シリコン結晶体構造の製造方法
JPH0682833B2 (ja) * 1985-02-08 1994-10-19 株式会社東芝 サイリスタの製造方法
JPH0770474B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 化合物半導体装置の製造方法
JPH0770476B2 (ja) * 1985-02-08 1995-07-31 株式会社東芝 半導体装置の製造方法
US4703553A (en) * 1986-06-16 1987-11-03 Spectrolab, Inc. Drive through doping process for manufacturing low back surface recombination solar cells
JP2579979B2 (ja) * 1987-02-26 1997-02-12 株式会社東芝 半導体素子の製造方法
US4837177A (en) * 1987-12-28 1989-06-06 Motorola Inc. Method of making bipolar semiconductor device having a conductive recombination layer
US4931408A (en) * 1989-10-13 1990-06-05 Siliconix Incorporated Method of fabricating a short-channel low voltage DMOS transistor

Also Published As

Publication number Publication date
DE69120857D1 (de) 1996-08-22
JPH04226010A (ja) 1992-08-14
JP3073257B2 (ja) 2000-08-07
KR100201744B1 (ko) 1999-06-15
EP0454236A1 (de) 1991-10-30
US5688714A (en) 1997-11-18
NL9000972A (nl) 1991-11-18
EP0454236B1 (de) 1996-07-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee