GB2300753A - Reducing the minority carrier lifetime of semiconductor devices - Google Patents

Reducing the minority carrier lifetime of semiconductor devices Download PDF

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Publication number
GB2300753A
GB2300753A GB9603635A GB9603635A GB2300753A GB 2300753 A GB2300753 A GB 2300753A GB 9603635 A GB9603635 A GB 9603635A GB 9603635 A GB9603635 A GB 9603635A GB 2300753 A GB2300753 A GB 2300753A
Authority
GB
United Kingdom
Prior art keywords
substrate
front surface
ions
minority carrier
carrier lifetime
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9603635A
Other versions
GB9603635D0 (en
Inventor
David James Chivers
Raymond Izzard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Atomic Energy Authority
Ricardo AEA Ltd
Original Assignee
AEA Technology PLC
UK Atomic Energy Authority
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB9509301.9A external-priority patent/GB9509301D0/en
Application filed by AEA Technology PLC, UK Atomic Energy Authority filed Critical AEA Technology PLC
Priority to GB9603635A priority Critical patent/GB2300753A/en
Publication of GB9603635D0 publication Critical patent/GB9603635D0/en
Publication of GB2300753A publication Critical patent/GB2300753A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers

Abstract

The front surfaces of selected regions (5) are implanted with ions, such as noble metals (eg gold), which have the property of reducing minority carrier lifetimes and the ions are caused to migrate a short distance into the implanted regions by subjecting the front surface of the device to a pulse of thermal energy.

Description

An Improved Process for the production of Semi Conductor Devices The present invention relates to the production of semiconductor devices, and in particular, to the production of semiconductor devices including switching elements - There are two principal ways of increasing the switching rate of semiconductor devices; one is by reducing the dimensions of the devices, and the other is by reducing the minority carrier lifetimes. The second of these parameters also is of importance in the case of semiconductor devices which are required to handle relatively large power levels. It is well known that the minority carrier lifetime can be controlled by doping the semiconductor material out of which the devices are made so as to provIde traps for the minority charge carriers in the semiconductor material.In the case of silicon based devices suitable dopants are gold or platinum. The dose levels required are much lower than those used in the fabrication of the switching and other circuit elements incorporated in the devices and conventionally the doping is achieved by depositing a coating of the noble metal on the back surface of the silicon wafer upon which the switching and other circuit elements are formed, remov ng the majority of the coating and thermally diffusing the remaining noble metal through the silicon wafer. This process is neither very repeatable nor easy to control. An alternative method is described in a paper "Control of Minority Carrier Lifetime by Gold Implantation in Semiconductor Devices" by S. Coffa et al.
J. Electrochem Soc. Vol 136 No 7 July 1989 pp 2073-2075.
In this method, gold is introduced into silicon wafers by means of ion implantation, which is far more controllable and well-defined than the previously described process. However, in this method also, the gold is implanted into the back face of the wafer and diffused thermally through the wafer to the front surface where it is required.
A great disadvantage of both these processes is the diffusion step because a) it has to be done at an early stage of the device production process, and b) the gold permeates the whole of the silicon wafer and degrades the electrical properties of the silicon in regions where a short minority carrier lifetime is not necessarily required and may, in fact, be harmful.
It is an object of the present invention to provide an improved method for the manufacture of semiconductor devices.
According to the present invention there is provided a method of menufacturing a semiconductor device including a substrate having a front surface region in which electrical elements are formed wherein there are included the operations of implanting into selected regions of the front surface of the substrate ions of a material adapted to reduce the minority carrier lifetime of the substrate material and subjecting the front surface of the substrate to a pulse of thermal energy sufficient to distribute the implanted ions throughout the selected regions of the substrate but insufficient to cause deleterious diffusion of the implanted material into other regions of the substrate.
Suitable materials for reducing the minority carrier lifetime in silicon are the noble metals, particularly gold, and suitable ion doses are in the region of 10" to 1014 ions/cm In the case of silicon, the amount of thermal energy in the thermo pulse should not exceed 5000 minutes, with a maximum temperature of about 10000C.
The invention will now be described, by way of example, with reference to the accompanying drawing which is a representation of the stages of a process embodying the invention.
Referring to the drawing, a portion of a wafer 1 of semiconductor material has a front surface 2 and a back surface 3. In he front surface 2 are a number of differently doped regions 4 which form components of electrical circuit elements in the normal way. The regions 4 are separated by other regions 5 in which it is desired to reduce the minority carrier lifetime of the material out of which the substrate 1 is made. In the first stage (a) of a process embodying the invention, the front surface 2 of the wafer 1 is cleaned by methods well-known in the semiconductor art and which it is not thought necessary to describe.Next, stage (b), those regions of the front surface 2 of the substrate 1 in which it is not desired that the minority carrier lifetime of the substrate 1 should be reduced, are protected by weans of a mask 6 formed on the front surface 2 of the substrate 1 by photolithographic techniques, which again are well known in the semiconductor art, and are not described herein. In the third stage () of the process, the front surface 2 of the wafer 1 is subjected to bombardment with a beam 7 of gold ions until a desired ion dose has been implanted in the exposed regions 5 of the surface 2 of the substrate 1.As the minority carrier lifetime is inversely related to the concentration of gold in the substrate, the ion dose is selected according to the minority carrier lifetime required, but normally the ion dose is in the range 1011 - 10l4 ions/cm2. A suitable ion energy is of the order of 80KeV. After the ion implantation has been completed, the substrate 1 is subjected to a pulse of thermal energy to allow the implanted ions to migrate a short distance, about 20R, into the substrate 1, stage (d). Both the time and temperature are controlled to ensure that sideways diffusion of the gold does not occur. In order to ensure this the integrated thermal energy should not exceed about 5000 minutes. The thermal pulse is applIed to front surface 2 of the substrate 1 is by a pulsed beart. of radiant energy, which may be from a laser. However, the entire wafer may be heated in a muffle furnace if preferred. Finally, the mask 6 is removed, stage (e).
By way of example, in a specific process, the following parameters were used: a) Substrate material:- Silicon b) Implanted ions:- Gold c) Ion dose:- 1 x 10'3 d) Thermal pulse:- 9000C for 30 minutes

Claims (10)

  1. Claims 1. A method of manufacturing a semiconductor device including a substrate having a front surface region in which electrical elements are formed wherein there are included the operations of implanting into selected regions of the front surface of the substrate ions of a material adapted to reduce the minority carrier lifetime of the substrate material and subjecting the front surface of the substrate to a pulse of thermal energy sufficient to distribute the implanted ions throughout the selected regions of the substrate but insufficient to cause deleterious diffusion of the implanted material into other regions of the substrate.
  2. 2. A method according to Claim 1 wherein the fluence of implanted ions is in the range 1011 to 1014 ions/cm2.
  3. 3. A method according to Claim 1 or Claim 2 wherein the substrate is made of silicon.
  4. 4. A method according to any of Claims 1 to 3 wherein the implanted material is a noble metal.
  5. 5. A method according to any preceding claim wherein the pulse of thermal energy is such as to provide an integrated temperature within the front surface region of the substrate of less than 5000C minutes.
  6. 6. A method according to Claim 5 wherein the maximum temperature of the front surface region of the substrate is less than 10000C.
  7. 7. A method according to Claim 1 wherein the substrate is made of silicon, the material adapted to reduce the minority carrier lifetime in the substrate material is gold, the ion fluence is 1013 ions/cm2, and the front surface region of the substrate is heated to a temperature of 9000C for a period of thirty minutes.
  8. 8. A method according to any preceding claim wherein the front surface of the substrate is heated by subjecting it to a pulse of radiant energy.
  9. 9. A method according to Claim 8 wherein the radiant energy is produced by a laser.
  10. 10. A method of reducing the minority carrier lifetime in a semiconductor device substantially as hereinbefore described and with reference to the accompanying drawings.
GB9603635A 1995-05-06 1996-02-21 Reducing the minority carrier lifetime of semiconductor devices Withdrawn GB2300753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9603635A GB2300753A (en) 1995-05-06 1996-02-21 Reducing the minority carrier lifetime of semiconductor devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9509301.9A GB9509301D0 (en) 1995-05-06 1995-05-06 An improved process for the production of semi-conductor devices
GB9603635A GB2300753A (en) 1995-05-06 1996-02-21 Reducing the minority carrier lifetime of semiconductor devices

Publications (2)

Publication Number Publication Date
GB9603635D0 GB9603635D0 (en) 1996-04-17
GB2300753A true GB2300753A (en) 1996-11-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB9603635A Withdrawn GB2300753A (en) 1995-05-06 1996-02-21 Reducing the minority carrier lifetime of semiconductor devices

Country Status (1)

Country Link
GB (1) GB2300753A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3655457A (en) * 1968-08-06 1972-04-11 Ibm Method of making or modifying a pn-junction by ion implantation
US4047976A (en) * 1976-06-21 1977-09-13 Motorola, Inc. Method for manufacturing a high-speed semiconductor device
GB2028580A (en) * 1978-08-23 1980-03-05 Sony Corp Ion implantation methods for semiconductor substrates

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3655457A (en) * 1968-08-06 1972-04-11 Ibm Method of making or modifying a pn-junction by ion implantation
US4047976A (en) * 1976-06-21 1977-09-13 Motorola, Inc. Method for manufacturing a high-speed semiconductor device
GB2028580A (en) * 1978-08-23 1980-03-05 Sony Corp Ion implantation methods for semiconductor substrates

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE Transactions on Electron Devices, vol 39, no 12, Dec 92MF Catiana et al, pp 2745-2749 *
Journal of Applied Physics, vol 74, no 1, 1/7/93, S Coffa etal, pp 195-200 *

Also Published As

Publication number Publication date
GB9603635D0 (en) 1996-04-17

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730 Substitution of applicants allowed (sect. 30/1977)
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)