DE112021002612T5 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung Download PDF

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Publication number
DE112021002612T5
DE112021002612T5 DE112021002612.7T DE112021002612T DE112021002612T5 DE 112021002612 T5 DE112021002612 T5 DE 112021002612T5 DE 112021002612 T DE112021002612 T DE 112021002612T DE 112021002612 T5 DE112021002612 T5 DE 112021002612T5
Authority
DE
Germany
Prior art keywords
active
region
peripheral
semiconductor device
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112021002612.7T
Other languages
German (de)
English (en)
Inventor
Daisuke Ozaki
Seiji Noguchi
Yosuke Sakurai
Ryutaro Hamasaki
Takuya Yamada
Yoshihiro Ikura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of DE112021002612T5 publication Critical patent/DE112021002612T5/de
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE112021002612.7T 2021-01-25 2021-10-04 Halbleitervorrichtung Pending DE112021002612T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021-009648 2021-01-25
JP2021009648 2021-01-25
PCT/JP2021/036687 WO2022158053A1 (ja) 2021-01-25 2021-10-04 半導体装置

Publications (1)

Publication Number Publication Date
DE112021002612T5 true DE112021002612T5 (de) 2023-03-16

Family

ID=82548676

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112021002612.7T Pending DE112021002612T5 (de) 2021-01-25 2021-10-04 Halbleitervorrichtung

Country Status (5)

Country Link
US (1) US12575149B2 (https=)
JP (1) JP7459976B2 (https=)
CN (1) CN115769382A (https=)
DE (1) DE112021002612T5 (https=)
WO (1) WO2022158053A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022158053A1 (ja) 2021-01-25 2022-07-28 富士電機株式会社 半導体装置
JP7593511B2 (ja) * 2022-01-20 2024-12-03 富士電機株式会社 半導体装置
JP2024034141A (ja) * 2022-08-31 2024-03-13 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2025142731A1 (ja) * 2023-12-28 2025-07-03 ローム株式会社 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019091892A (ja) 2017-10-24 2019-06-13 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ ｄＶ／ｄｔ制御性を備えたＩＧＢＴ
JP2019110288A (ja) 2017-10-24 2019-07-04 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ ｄＶ／ｄｔ制御性を備えたＩＧＢＴを製造する方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4028333B2 (ja) * 2002-09-02 2007-12-26 株式会社東芝 半導体装置
JP3934613B2 (ja) 2004-01-21 2007-06-20 株式会社東芝 半導体装置
US8519477B2 (en) * 2009-11-20 2013-08-27 Force Mos Technology Co., Ltd. Trench MOSFET with trenched floating gates and trenched channel stop gates in termination
US8680613B2 (en) * 2012-07-30 2014-03-25 Alpha And Omega Semiconductor Incorporated Termination design for high voltage device
MX2014003783A (es) 2011-09-28 2014-05-14 Toyota Motor Co Ltd Igbt y metodo para fabricar el mismo.
WO2013080806A1 (ja) 2011-11-28 2013-06-06 富士電機株式会社 絶縁ゲート型半導体装置およびその製造方法
US8829607B1 (en) * 2013-07-25 2014-09-09 Fu-Yuan Hsieh Fast switching super-junction trench MOSFETs
JP6208579B2 (ja) * 2013-12-26 2017-10-04 トヨタ自動車株式会社 半導体装置
JP6231396B2 (ja) 2014-02-10 2017-11-15 トヨタ自動車株式会社 半導体装置及び半導体装置の製造方法
JP6472714B2 (ja) 2015-06-03 2019-02-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6728953B2 (ja) * 2015-07-16 2020-07-22 富士電機株式会社 半導体装置及びその製造方法
CN108140674B (zh) 2015-10-16 2021-02-19 三菱电机株式会社 半导体装置
DE102016112721B4 (de) 2016-07-12 2022-02-03 Infineon Technologies Ag n-Kanal-Leistungshalbleitervorrichtung mit p-Schicht im Driftvolumen
DE102017107174B4 (de) 2017-04-04 2020-10-08 Infineon Technologies Ag IGBT mit dV/dt-Steuerbarkeit und Verfahren zum Verarbeiten eines IGBT
JP6946824B2 (ja) * 2017-07-28 2021-10-06 富士電機株式会社 半導体装置および半導体装置の製造方法
WO2020078626A1 (en) 2018-10-18 2020-04-23 Abb Schweiz Ag Insulated gate power semiconductor device and method for manufacturing such device
WO2022158053A1 (ja) 2021-01-25 2022-07-28 富士電機株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019091892A (ja) 2017-10-24 2019-06-13 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ ｄＶ／ｄｔ制御性を備えたＩＧＢＴ
JP2019110288A (ja) 2017-10-24 2019-07-04 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ ｄＶ／ｄｔ制御性を備えたＩＧＢＴを製造する方法

Also Published As

Publication number Publication date
US12575149B2 (en) 2026-03-10
JPWO2022158053A1 (https=) 2022-07-28
CN115769382A (zh) 2023-03-07
WO2022158053A1 (ja) 2022-07-28
JP7459976B2 (ja) 2024-04-02
US20230124922A1 (en) 2023-04-20

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