DE112016000307A5 - Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses - Google Patents

Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses Download PDF

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Publication number
DE112016000307A5
DE112016000307A5 DE112016000307.2T DE112016000307T DE112016000307A5 DE 112016000307 A5 DE112016000307 A5 DE 112016000307A5 DE 112016000307 T DE112016000307 T DE 112016000307T DE 112016000307 A5 DE112016000307 A5 DE 112016000307A5
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DE
Germany
Prior art keywords
manufacturing
lead frame
chip package
package
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE112016000307.2T
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English (en)
Other versions
DE112016000307B4 (de
Inventor
Martin Brandl
Tobias Gebuhr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of DE112016000307A5 publication Critical patent/DE112016000307A5/de
Application granted granted Critical
Publication of DE112016000307B4 publication Critical patent/DE112016000307B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE112016000307.2T 2015-01-09 2016-01-07 Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses sowie Verfahren zum Herstellen eines optoelektronischen Bauelements Active DE112016000307B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102015100262.0A DE102015100262A1 (de) 2015-01-09 2015-01-09 Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses sowie Verfahren zum Herstellen eines optoelektronischen Bauelements
DE102015100262.0 2015-01-09
PCT/EP2016/050221 WO2016110545A1 (de) 2015-01-09 2016-01-07 Leiterrahmen und verfahren zum herstellen eines chipgehäuses

Publications (2)

Publication Number Publication Date
DE112016000307A5 true DE112016000307A5 (de) 2017-09-28
DE112016000307B4 DE112016000307B4 (de) 2023-04-27

Family

ID=55072665

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102015100262.0A Withdrawn DE102015100262A1 (de) 2015-01-09 2015-01-09 Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses sowie Verfahren zum Herstellen eines optoelektronischen Bauelements
DE112016000307.2T Active DE112016000307B4 (de) 2015-01-09 2016-01-07 Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses sowie Verfahren zum Herstellen eines optoelektronischen Bauelements

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE102015100262.0A Withdrawn DE102015100262A1 (de) 2015-01-09 2015-01-09 Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses sowie Verfahren zum Herstellen eines optoelektronischen Bauelements

Country Status (5)

Country Link
US (1) US10297537B2 (de)
JP (1) JP6442611B2 (de)
DE (2) DE102015100262A1 (de)
TW (1) TWI686909B (de)
WO (1) WO2016110545A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015100262A1 (de) * 2015-01-09 2016-07-14 Osram Opto Semiconductors Gmbh Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses sowie Verfahren zum Herstellen eines optoelektronischen Bauelements
DE102017123898A1 (de) * 2017-10-13 2019-04-18 Osram Opto Semiconductors Gmbh Halbleiterbauelement und Verfahren zur Herstellung von Halbleiterbauelementen
TWI754971B (zh) * 2020-06-23 2022-02-11 新加坡商光寶科技新加坡私人有限公司 感測元件封裝結構及其封裝方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57118658A (en) * 1981-12-07 1982-07-23 Hitachi Ltd Lead frame
JPS63148670A (ja) 1986-12-12 1988-06-21 Texas Instr Japan Ltd リ−ドフレ−ム材
JP2681144B2 (ja) * 1989-08-19 1997-11-26 三菱電機株式会社 半導体装置用リードフレーム
JP3167769B2 (ja) * 1992-01-16 2001-05-21 シャープ株式会社 リードフレームおよびこれを利用した光学装置の製造方法
US5789806A (en) * 1995-08-02 1998-08-04 National Semiconductor Corporation Leadframe including bendable support arms for downsetting a die attach pad
US20080157297A1 (en) * 2006-12-29 2008-07-03 Takahiko Kudoh Stress-Resistant Leadframe and Method
JP4205135B2 (ja) 2007-03-13 2009-01-07 シャープ株式会社 半導体発光装置、半導体発光装置用多連リードフレーム
US20110001227A1 (en) 2009-07-01 2011-01-06 Texas Instruments Incorporated Semiconductor Chip Secured to Leadframe by Friction
CN102222625A (zh) * 2010-04-16 2011-10-19 展晶科技(深圳)有限公司 发光二极管封装结构及其基座的制造方法
US8735671B2 (en) * 2011-07-29 2014-05-27 Monsanto Technology Llc Soybean variety A1026046
DE102011056706B4 (de) * 2011-12-20 2016-12-15 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen, Anordnung und optoelektronisches Halbleiterbauteil
JP5888098B2 (ja) * 2012-04-27 2016-03-16 大日本印刷株式会社 Ｌｅｄ素子搭載用リードフレーム、樹脂付リードフレーム、多面付ｌｅｄパッケージ、ｌｅｄパッケージの製造方法および半導体素子搭載用リードフレーム
JP5947107B2 (ja) * 2012-05-23 2016-07-06 ルネサスエレクトロニクス株式会社 半導体装置
DE102012104882B4 (de) * 2012-06-05 2017-06-08 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen und damit hergestelltes optoelektronisches Halbleiterbauteil
JP6241238B2 (ja) * 2013-01-11 2017-12-06 株式会社カネカ 発光素子実装用リードフレーム、樹脂成型体及び表面実装型発光装置
DE102013211223A1 (de) * 2013-06-14 2014-12-18 Osram Gmbh Leadframe für eine Leuchtvorrichtung
DE102013211233A1 (de) 2013-06-17 2014-12-18 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Optische Bauelemente und Verfahren zu deren Herstellung
JP6357415B2 (ja) * 2014-12-26 2018-07-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE102015100262A1 (de) * 2015-01-09 2016-07-14 Osram Opto Semiconductors Gmbh Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses sowie Verfahren zum Herstellen eines optoelektronischen Bauelements
US20160276185A1 (en) * 2015-03-17 2016-09-22 Texas Instruments Incorporated Method and apparatus for making integrated circuit packages

Also Published As

Publication number Publication date
TWI686909B (zh) 2020-03-01
JP2018501655A (ja) 2018-01-18
US10297537B2 (en) 2019-05-21
US20180005924A1 (en) 2018-01-04
DE102015100262A1 (de) 2016-07-14
WO2016110545A1 (de) 2016-07-14
JP6442611B2 (ja) 2018-12-19
TW201637162A (zh) 2016-10-16
DE112016000307B4 (de) 2023-04-27

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