DE102015110144B8 - Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips - Google Patents

Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips Download PDF

Info

Publication number
DE102015110144B8
DE102015110144B8 DE102015110144.0A DE102015110144A DE102015110144B8 DE 102015110144 B8 DE102015110144 B8 DE 102015110144B8 DE 102015110144 A DE102015110144 A DE 102015110144A DE 102015110144 B8 DE102015110144 B8 DE 102015110144B8
Authority
DE
Germany
Prior art keywords
chip
testing
processing component
component
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102015110144.0A
Other languages
English (en)
Other versions
DE102015110144B4 (de
DE102015110144A1 (de
Inventor
Daniel Tille
Ulrike Pfannkuchen
Markus Janke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102015110144.0A priority Critical patent/DE102015110144B8/de
Priority to US15/191,553 priority patent/US20160377677A1/en
Publication of DE102015110144A1 publication Critical patent/DE102015110144A1/de
Publication of DE102015110144B4 publication Critical patent/DE102015110144B4/de
Application granted granted Critical
Publication of DE102015110144B8 publication Critical patent/DE102015110144B8/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE102015110144.0A 2015-06-24 2015-06-24 Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips Active DE102015110144B8 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE102015110144.0A DE102015110144B8 (de) 2015-06-24 2015-06-24 Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips
US15/191,553 US20160377677A1 (en) 2015-06-24 2016-06-24 Chip and method for testing a processing component of a chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102015110144.0A DE102015110144B8 (de) 2015-06-24 2015-06-24 Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips

Publications (3)

Publication Number Publication Date
DE102015110144A1 DE102015110144A1 (de) 2016-12-29
DE102015110144B4 DE102015110144B4 (de) 2018-04-05
DE102015110144B8 true DE102015110144B8 (de) 2018-06-28

Family

ID=57536965

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102015110144.0A Active DE102015110144B8 (de) 2015-06-24 2015-06-24 Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips

Country Status (2)

Country Link
US (1) US20160377677A1 (de)
DE (1) DE102015110144B8 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10473711B2 (en) * 2016-04-15 2019-11-12 Infineon Technologies Ag Multi-channel fault detection with a single diagnosis output
CN108073831B (zh) * 2016-11-15 2020-07-24 华为技术有限公司 一种检测安全芯片工作状态的方法及检测电路
US10908213B1 (en) * 2018-09-28 2021-02-02 Synopsys, Inc. Reducing X-masking effect for linear time compactors
US20220179929A1 (en) * 2020-12-09 2022-06-09 Synopsys, Inc. Obfuscating encrypted register transfer logic model of a circuit
CN113986600B (zh) * 2021-11-04 2023-02-03 北京智芯微电子科技有限公司 一种用于芯片串行接口的测试方法、装置和芯片

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602004009329T2 (de) * 2003-09-26 2008-07-10 Nxp B.V. Verfahren und system zum selektiven maskieren von testantworten

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4228061B2 (ja) * 2000-12-07 2009-02-25 富士通マイクロエレクトロニクス株式会社 集積回路の試験装置および試験方法
US6901546B2 (en) * 2001-06-07 2005-05-31 International Business Machines Corporation Enhanced debug scheme for LBIST
US7228474B2 (en) * 2003-01-07 2007-06-05 Sun Microsystems, Inc. Semiconductor device and method and apparatus for testing such a device
US20040139377A1 (en) * 2003-01-13 2004-07-15 International Business Machines Corporation Method and apparatus for compact scan testing
FR2865827A1 (fr) * 2004-01-29 2005-08-05 St Microelectronics Sa Securisation du mode de test d'un circuit integre
US7451373B2 (en) * 2005-06-17 2008-11-11 Infineon Technologies Ag Circuit for compression and storage of circuit diagnosis data
FR2897439A1 (fr) * 2006-02-15 2007-08-17 St Microelectronics Sa Circuit elelctronique comprenant un mode de test securise par l'utilisation d'un identifiant, et procede associe
CN101405609B (zh) * 2006-02-17 2012-11-14 明导公司 多级测试响应压缩器
US8166359B2 (en) * 2007-12-20 2012-04-24 Mentor Graphics Corporation Selective per-cycle masking of scan chains for system level test
WO2010060012A1 (en) * 2008-11-23 2010-05-27 Mentor Graphics Corporation On-chip logic to support in-field or post-tape-out x-masking in bist designs
US20120119112A1 (en) * 2010-10-13 2012-05-17 Susan Houde-Walter Thermal marking systems and methods of control
EP2608039B1 (de) * 2011-12-22 2014-05-21 Nxp B.V. Sichere Abtastung mit niedriger Pinzahl
US9599673B2 (en) * 2014-10-15 2017-03-21 Freescale Semiconductor, Inc. Structural testing of integrated circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602004009329T2 (de) * 2003-09-26 2008-07-10 Nxp B.V. Verfahren und system zum selektiven maskieren von testantworten

Also Published As

Publication number Publication date
DE102015110144B4 (de) 2018-04-05
DE102015110144A1 (de) 2016-12-29
US20160377677A1 (en) 2016-12-29

Similar Documents

Publication Publication Date Title
DE112017005822A5 (de) Multipixel-led-bauteil und verfahren zum betreiben eines multipixel-led-bauteils
DE102015119413A8 (de) Verfahren zum Bearbeiten eines Halbleitersubstrats und Verfahren zum Bearbeiten eines Halbleiterwafers
DE112018001263A5 (de) Verfahren zum Betreiben eines optoelektronischen Bauelements und optoelektronisches Bauelement
DE102016209675A8 (de) Verfahren und System zum Herstellen eines Kleidungsstücks
DE112015005964A5 (de) Bauelement und Verfahren zur Herstellung eines Bauelements
DE102015110144B8 (de) Chip und Verfahren zum Testen einer Verarbeitungskomponente eines Chips
DE112016002595A5 (de) Verfahren zum betrieb eines umdrehungssensors und entsprechender umdrehungssensor
DE102015119707B8 (de) Verfahren zum Ausrichten eines Laserscanners und Laserscanneranordnung
DE112014005278A5 (de) Vorrichtung und Verfahren zum Lösen eines ersten Substrats
DE112015000824A5 (de) Verfahren zur Herstellung eines elektronischen Halbleiterchips und elektronischer Halbleiterchip
DE112016000626A5 (de) Verfahren und vorrichtung zur überprüfung einer optoelektronischen komponente
DE112016002148A5 (de) Verfahren zum Bearbeiten eines Leiterrahmens und Leiterrahmen
DE102014102565A8 (de) Optoelektronisches Bauelement und Verfahren zum Herstellen eines optoelektronischen Bauelements
DE112018002085A5 (de) Verfahren zum Befestigen eines Halbleiterchips auf einem Leiterrahmen und elektronisches Bauelement
DE112016001670A5 (de) Bauelement und Verfahren zur Herstellung eines Bauelements
DE112017003878A5 (de) Verfahren und Vorrichtung zur Vermessung einer Vielzahl an Halbleiterchips in einem Waferverbund
DE112017000758A5 (de) Vorrichtung und Verfahren zur Ermittlung einer Objektkinematik eines beweglichen Objektes
DE112016003555A5 (de) Vorrichtung zum Transportieren eines Transportgutes und Verfahren
DE112018001835A5 (de) Verfahren zum Herstellen eines optoelektronischen Halbleiterbauelements und optoelektronisches Halbleiterbauelement
DE112017003099A5 (de) Optoelektronisches bauelement und verfahren zum herstellen eines optoelektronischen bauelements
DE112016003331A5 (de) Optoelektronisches Bauteil und Verfahren zum Betrieb eines optoelektronischen Bauteils
DE112015002211A5 (de) Oberflächenmontierbares optoelektronisches Bauelement und Verfahren zum Herstellen eines oberflächenmontierbaren optoelektronischen Bauelements
DE112017001889A5 (de) Optoelektronisches Bauelement und Verfahren zum Herstellen eines optoelektronischen Bauelements
DE102014208319A8 (de) Bandfinishvorrichtung und Verfahren zum Betrieb einer Bandfinishvorrichtung
DE112016000307A5 (de) Leiterrahmen und Verfahren zum Herstellen eines Chipgehäuses

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R082 Change of representative

Representative=s name: VIERING, JENTSCHURA & PARTNER MBB PATENT- UND , DE

R020 Patent grant now final
R082 Change of representative