DE102013103860A8 - Chipgehäuse und Verfahren zum Bilden desselben - Google Patents
Chipgehäuse und Verfahren zum Bilden desselben Download PDFInfo
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- DE102013103860A8 DE102013103860A8 DE102013103860A DE102013103860A DE102013103860A8 DE 102013103860 A8 DE102013103860 A8 DE 102013103860A8 DE 102013103860 A DE102013103860 A DE 102013103860A DE 102013103860 A DE102013103860 A DE 102013103860A DE 102013103860 A8 DE102013103860 A8 DE 102013103860A8
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
- H01L2924/13034—Silicon Controlled Rectifier [SCR]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
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- H01L2924/181—Encapsulation
Applications Claiming Priority (2)
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US13/454,115 | 2012-04-24 | ||
US13/454,115 US8945990B2 (en) | 2012-04-24 | 2012-04-24 | Chip package and method of forming the same |
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DE102013103860A1 DE102013103860A1 (de) | 2013-10-24 |
DE102013103860A8 true DE102013103860A8 (de) | 2013-12-05 |
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DE102013103860A Pending DE102013103860A1 (de) | 2012-04-24 | 2013-04-17 | Chipgehäuse und Verfahren zum Bilden desselben |
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US (1) | US8945990B2 (de) |
CN (1) | CN103377957B (de) |
DE (1) | DE102013103860A1 (de) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20130341780A1 (en) * | 2012-06-20 | 2013-12-26 | Infineon Technologies Ag | Chip arrangements and a method for forming a chip arrangement |
US9330993B2 (en) | 2012-12-20 | 2016-05-03 | Intel Corporation | Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby |
US9076783B2 (en) * | 2013-03-22 | 2015-07-07 | Freescale Semiconductor, Inc. | Methods and systems for selectively forming metal layers on lead frames after die attachment |
KR20160048277A (ko) * | 2014-10-23 | 2016-05-04 | 에스케이하이닉스 주식회사 | 칩 내장 패키지 및 그 제조방법 |
DE102014117410B4 (de) * | 2014-11-27 | 2019-01-03 | Heraeus Deutschland GmbH & Co. KG | Elektrisches Kontaktelement, Einpressstift, Buchse und Leadframe |
DE102016103585B4 (de) * | 2016-02-29 | 2022-01-13 | Infineon Technologies Ag | Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt |
JP3238263U (ja) | 2019-07-25 | 2022-07-13 | ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト | パワー半導体モジュール |
TW202236570A (zh) * | 2021-03-12 | 2022-09-16 | 華東科技股份有限公司 | 系統級封裝 |
TWI791200B (zh) * | 2021-03-12 | 2023-02-01 | 華東科技股份有限公司 | 薄型系統級封裝 |
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US4499152A (en) * | 1982-08-09 | 1985-02-12 | General Electric Company | Metal-clad laminate construction |
JP3801188B2 (ja) * | 2004-09-06 | 2006-07-26 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
US7507605B2 (en) * | 2004-12-30 | 2009-03-24 | Texas Instruments Incorporated | Low cost lead-free preplated leadframe having improved adhesion and solderability |
KR100642889B1 (ko) * | 2005-05-25 | 2006-11-03 | 엘에스전선 주식회사 | 반도체용 접착필름 |
DE102007045794A1 (de) | 2006-09-27 | 2008-04-17 | MEC Co., Ltd., Amagasaki | Haftvermittler für Harz und Verfahren zur Erzeugung eines Laminates, umfassend den Haftvermittler |
JP5605222B2 (ja) * | 2008-05-09 | 2014-10-15 | 国立大学法人九州工業大学 | 3次元実装半導体装置及びその製造方法 |
KR101095119B1 (ko) * | 2009-08-19 | 2011-12-16 | 삼성전기주식회사 | 다이 패키지 및 그 제조방법 |
US8513062B2 (en) | 2010-02-16 | 2013-08-20 | Infineon Technologies Ag | Method of manufacturing a semiconductor device with a carrier having a cavity and semiconductor device |
JP2012216773A (ja) * | 2011-03-29 | 2012-11-08 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
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2012
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2013
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DE102013103860A1 (de) | 2013-10-24 |
CN103377957B (zh) | 2017-06-13 |
CN103377957A (zh) | 2013-10-30 |
US8945990B2 (en) | 2015-02-03 |
US20130277813A1 (en) | 2013-10-24 |
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