CN103377957B - 芯片封装及形成芯片封装的方法 - Google Patents

芯片封装及形成芯片封装的方法 Download PDF

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Publication number
CN103377957B
CN103377957B CN201310145102.8A CN201310145102A CN103377957B CN 103377957 B CN103377957 B CN 103377957B CN 201310145102 A CN201310145102 A CN 201310145102A CN 103377957 B CN103377957 B CN 103377957B
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chip
carrier
adhesive layer
tin
layers
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CN103377957A (zh
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吴顺禄
李瑞家
M.门格尔
S.施密德
H.托尔维斯滕
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及芯片封装及形成芯片封装的方法。实施例提供了一种形成芯片封装的方法。方法可以包括：在载体上附着至少一个芯片，该芯片包括与载体相对的芯片表面上的多个芯片焊盘；在载体和芯片的芯片焊盘上沉积第一粘合层，第一粘合层包括锡或铟；在第一粘合层上沉积第二粘合层，第二粘合层包括硅烷有机材料；以及在第二粘合层和芯片上沉积层压层或密封层。

Description

芯片封装及形成芯片封装的方法
技术领域
实施例一般地涉及一种芯片封装以及形成芯片封装的方法。
背景技术
在例如针对功率模块的芯片嵌入封装技术中，在芯片已经被安装到衬底上（“管芯附着”）之后用层压层（laminate）嵌入芯片，而芯片正面处的源和栅接触借助于激光被打开，并且随后被电镀地填充。
为了实现层压层到铜衬底的更好的粘合，在层压之前经常借助于湿法化学工艺来使铜衬底变粗糙和起纹理。在那个情况下，刻蚀化学应该被设置为使得芯片连接材料、例如扩散焊料或导电粘合剂不溶解。此外，芯片的有源正面不应该借助于起纹理工艺（texturing process）被损坏。芯片载体材料与层压层之间的粘合应该经受住发生在例如温度循环、高温、存储和湿法存储（wet-storing）时的应力负荷。
粗糙化工艺或起纹理工艺的一个方法是使用不同的化学品，尤其是借助于（为未知的有机物的）强刻蚀硫酸以及过氧化氢等。在该方法中，具有被安装的组件的衬底被给到特定温度下的上面提及的化学品的浴（bath）中，并且达预定的时间周期。
然而，在常规的工艺中要求具有浓度和温度变化的复杂的浴处理，其也能引起粗糙度的变化，并且因而引起层压层到衬底的粘合的变化。供应商公司的有机成分是未知的，并且残余产物的效果是未知的。要求对于对应的衬底表面和引线框架（leadframe）镀覆（plating）的工艺设置。另外，存在芯片与衬底之间的区域的欠刻蚀的风险。在芯片焊盘-铜-金属化的刻蚀中，由于所要求的芯片焊盘上的更厚的铜层，招致更高的成本。需要刻蚀掉开口边缘处的铝芯片背面金属化，并且因而存在芯片背面金属化的粘合问题，特别是在应力负荷之后存在（所刻蚀的间隙中的刻蚀介质残余物引起湿度测试中的具有电化学腐蚀的局部元件）。此外，存在关于芯片粘合剂的选择的限制。
在芯片封装中，脱层（delamination）可能发生在模化合物（mold compound）与芯片载体之间，例如可能发生在模化合物与芯片载体上的引线框架之间。一个方法是使用诸如A2、moldPrep和uPPF之类的助促进剂（promoter）来增强模化合物与引线框架之间的粘合。然而，这些粘合助促进剂可能引起差的导线可接合性和高成本，其中粘合助促进剂残余的沾污可能影响导线可接合性。
发明内容
实施例提供了一种形成芯片封装的方法。方法可以包括：在载体上附着至少一个芯片，该芯片包括与载体相对的芯片表面上的多个芯片焊盘；在载体和芯片的芯片焊盘上沉积第一粘合层，该第一粘合层包括锡或铟；在第一粘合层上沉积第二粘合层，该第二粘合层包括硅烷有机材料；以及在第二粘合层和芯片上沉积层压层或密封层。
另一个实施例提供了一种形成芯片封装的方法。方法可以包括：在载体上附着至少一个芯片；形成芯片与载体之间的互连；在载体和互连上沉积锡层；在锡层和芯片上沉积密封层。
另一实施例提供了一种形成芯片封装的方法。方法可以包括：在所选择的载体区域上沉积包括锡材料的粘合层；在被沉积在所选择的载体区域中的至少一个上的粘合层上附着至少一个芯片；形成芯片与所选择的载体区域中的至少一个之间的互连；以及在载体、粘合层和芯片上沉积密封层。
附图说明
在图中，遍及不同的视图，相同的参考符号一般指的是相同的部分。图不必成比例，代之的是，一般强调图示本发明的原理。在下面的描述中，各种实施例参照下面的图被描述，在其中：
图1示出了图示了根据实施例的形成芯片封装的方法的流程图。
图2A至2F示出了用于形成根据实施例的芯片封装的工艺。
图3图示了根据实施例的粘合层与层压层/密封之间的化学接合。
图4示出了图示了根据另一个实施例的形成芯片封装的方法的流程图。
图5A至5D图示了根据另一个实施例的用于形成芯片封装的工艺。
图6示出了根据实施例的在锡层的沉积之前和之后的结构。
图7示出了图示了根据另一实施例的形成芯片封装的方法的流程图。
图8A至8C图示了根据一个实施例的用于形成芯片封装的工艺。
图9A至9C图示了根据另一个实施例的用于形成芯片封装的工艺。
图10示出了各种材料的IEPS值。
具体实施方式
各种实施例提供了具有层压层与芯片载体之间的良好粘合的可靠芯片封装（例如芯片嵌入封装）。
各种实施例提供了具有密封（encapsulation）与芯片封装之间的良好粘合以及良好的管芯/导线可接合性的健壮的芯片封装。
在形成芯片封装的方法的上下文中的下面所述的实施例针对通过使用各自的方法所形成的各自的芯片封装是类似地有效的，并且反之亦然。
在该上下文中，载体是芯片被安装和封装在其上的衬底。载体可以包括引线框架，并且可以包括金属（例如铜）或向芯片提供电连接和机械支撑的其它合适的材料（诸如铜合金或铁合金（ferrous alloy））。
在各种实施例中，多个芯片中的至少一个可以包括至少部分晶片衬底。可替换地，多个芯片中的每个都可以包括至少部分晶片衬底。多个芯片中的至少一个可以包括被形成在晶片衬底内的一个或多个电子电路，例如所述一个或多个电子电路可以通过更早的前端工艺已经被形成。多个芯片中的至少一个可能包括至少部分功率半导体芯片，其中功率半导体芯片可以包括来自由功率晶体管、功率MOS晶体管、功率双极晶体管、功率场效应晶体管、功率绝缘栅双极晶体管、晶闸管、MOS控制晶闸管、硅控制整流器、功率肖特基二极管、碳化硅二极管、氮化镓器件组成的组中的至少一个功率半导体器件。
可以理解的是，多个芯片可以不限于功率半导体器件，而是还可以包括逻辑器件，例如专用集成芯片ASIC或者诸如例如可编程微处理器（例如驱动器、例如控制器、例如传感器）之类的可编程处理器，和/或诸如包括易失和/或非易失存储器件的随机存取存储器件之类的存储器件。
一个实施例被引向形成芯片封装的方法。方法可以包括附着至少一个芯片在载体上，芯片包括与载体相对的芯片表面上的多个芯片焊盘；在载体和芯片的芯片焊盘上沉积第一粘合层，第一粘合层包括锡或铟；在第一粘合层上沉积第二粘合层，第二粘合层包括硅烷有机材料；以及在第二粘合层和芯片上沉积层压层或密封层。
在实施例中，在载体上附着至少一个芯片包括在引线框架上附着至少一个芯片。
在实施例中，芯片可以通过使用可印胶（printable paste）或管芯附着膜经由管芯接合来被附着在载体上。
在实施例中，第一粘合层可以包括纯锡。在另一个实施例中，第一粘合层可以包括锡合金，其中锡合金可以包括锡以及一个或多个其它金属。在一个实施例中，第一粘合层可以包括锡镍合金。在其它实施例中，第一粘合层可以包括锡铅合金、锡银合金或锡铜合金。
在另一个实施例中，第一粘合层可以包括纯铟。在另一实施例中，第一粘合层可以包括铟合金，其中铟合金可以包括铟以及一个或多个其它金属。
根据实施例，形成到所选择的芯片焊盘和所选择的载体区域的多个通孔，其中通孔延伸穿过层压层、第一粘合层和第二粘合层。在实施例中，多个通孔通过激光钻孔被形成。在另一个实施例中，可以通过机械钻孔或等离子刻蚀工艺来形成多个通孔。例如，所选择的芯片焊盘可以包括到芯片的一个或多个晶体管的源和/或漏的接触焊盘。
在实施例中，用导电材料电镀地填充多个通孔，以致实现到所选择的芯片焊盘和到所选择的载体区域的电连接。在另一实施例中，电连接被形成结构或形成图形以实现想要的电路图形。
根据实施例，层压层可以包括电介质膜材料。在实施例中，层压层可以包括涂树脂铜（resin-coated-copper）（RCC）材料。在另一个实施例中，层压层可以包括铜包覆层压层（copper clad laminate）。
根据另一个实施例，密封层可以包括密封材料。密封材料可以包括来自下面的材料的组中的至少一个，所述组由以下组成：填充的或未填充的环氧化物、预浸渍（pre-impregnated）复合纤维、加强的纤维、层压层、模材料、模化合物、热固材料、热塑材料、填充物颗粒、纤维加强的层压层、纤维加强的聚合物层压层、具有填充物颗粒的纤维加强的聚合物层压层。
另一个实施例被引向芯片封装。芯片封装可以包括：载体；被附着在载体上的至少一个芯片，芯片包括在与载体相对的芯片表面上的多个芯片焊盘；被部署在载体和芯片上的层压层或密封层；延伸穿过层压层或密封层到所选择的芯片焊盘和所选择的载体区域的多个通孔；以及被形成在载体与层压层或密封层之间、以及被形成在芯片焊盘与层压层或密封层之间的粘合层。粘合层包括硅烷有机材料。
在实施里中，载体可以包括引线框架。
另一实施例提供了形成芯片封装的方法。方法可以包括：在载体上附着至少一个芯片；形成芯片与载体之间的互连；在载体和互连上沉积锡层；以及在锡层和芯片上沉积密封层。
在实施例中，在载体上附着至少一个芯片包括在引线框架上附着至少一个芯片。
在另一实施例中，方法可以包括在载体下沉积锡层。
另一实施例提供了芯片封装。芯片封装包括：载体；被附着在载体上的至少一个芯片；芯片与载体之间的互连；被沉积在载体和互连上的锡层；以及被沉积在锡层和芯片上的密封层。
在实施例中，载体可以包括引线框架。
另一个另外的实施例提供了形成芯片封装的方法。方法可以包括：在所选择的载体区域上沉积包括锡材料的粘合层；在被沉积在所选择的载体区域中的至少一个上的粘合层上附着至少一个芯片；形成芯片与所选择的载体区域中的至少一个之间的互连；以及在载体、粘合层和芯片上沉积密封层。
在实施例中，在所选择的载体区域上沉积包括锡材料的粘合层可以包括在所选择的引线框架区域上沉积包括锡材料的粘合层。
在实施例中，方法可以进一步包括在载体下沉积粘合层。
根据一个实施例，粘合层可以包括锡银合金。在一个例子中，锡银合金可以包括80%的锡（Sn）和20%的银（Ag）。在另一个例子中，锡银合金可以包括20%到30%的银。在其它例子中，锡银合金可以包括具有诸如10/90 AgSn、30/70 AgSn、40/60 AgSn之类的其它比例的锡和银，其增强了到密封层的粘合强度。在实施例中，包括锡银合金的粘合层具有为至少2μm的厚度。
根据另一个实施例，粘合层可以包括具有锡和金之间的合适的比例的锡金合金，以致增强载体与模化合物之间的粘合强度。
根据另一实施例，粘合层可以包括被夹在第一银层与第二银层之间的锡层。在实施例中，锡层可以具有为约2μm到3μm的厚度；第一银层与载体接触，并且可以具有为约1μm到2μm的厚度；而第二银层可以具有为约0.1μm到1μm的厚度。第一银层可以防止载体材料（例如铜）到锡层的扩散。锡夹层可以增强粘合强度。第二银层可以能够实现导线接合以及芯片与载体之间的管芯接合。
在实施例中，方法可以进一步包括在载体下沉积粘合层。
另一实施例被引向芯片封装。芯片封装额可以包括：载体；包括锡材料并且被沉积在所选择的载体区域上的粘合层；被附着在被沉积在所选择的载体区域中的至少一个上的粘合层上的至少一个芯片；被形成在芯片与所选择的载体区域中的至少一个之间的互连；以及被沉积在载体、粘合层和芯片上的密封层。
在实施例中，载体可以包括引线框架。
图1示出了图示了根据实施例的形成芯片封装的方法的流程图。
在101，至少一个芯片被附着在载体上，其中芯片包括与载体相对的芯片表面上的多个芯片焊盘。在实施例中，芯片可以通过使用焊料或环氧化物接合的管芯接合来被附着在载体上。
在103，第一粘合层被沉积在载体和芯片的芯片芯片焊盘上。第一粘合层可以包括锡。
在105，第一粘合层被沉积在第一粘合层上。第二粘合层可以包括硅烷有机材料。
在107，层压层被沉积在第二粘合层和芯片上。
图2A至2F图示了根据实施例的用于形成芯片封装的工艺。
在图2A中，至少一个芯片203（只有一个芯片在该实施例中被示出）被附着在载体201上。芯片203可以通过使用焊料或环氧化物接合的管芯接合来被附着在载体201上。在实施例中，芯片203可以被附着在被形成为载体201的引线框架上。芯片203可以包括与载体201相对的芯片203表面上的多个芯片焊盘205。在实施例中，一个或多个芯片焊盘205可以是芯片203中的一个或多个晶体管的源或漏端子处的接触焊盘。
在实施例中，载体可以包括铜。在另一个实施例中，载体可以包括铜合金，诸如包括Cu、Cr、Sn、Zn的合金；或者包括Cu、Ni、Si、Zn、Ag的合金。在另一实施例中，载体可以包括铁合金。
在图2B中，第一粘合层207被沉积在载体201和芯片203的芯片焊盘205上。第一粘合层207可以包括锡或铟。在实施例中，第一粘合层可以包括纯锡。在另一个实施例中，第一粘合层207可以包括包括锡以及一个或多个其它金属的锡合金。在实施例中，第一粘合层207可以包括锡镍（Sn-Ni）合金，或者可以包括锡铅合金、锡银合金或锡铜合金。在另一个实施例中，第一粘合层207可以包括纯铟。在另一实施例中，第一粘合层207可以包括铟合金，其中铟合金可以包括铟以及一个或多个其它金属。
在实施例中，第一粘合层207通过Sn和Ni混合物的化学沉积被形成在载体201和芯片焊盘205上。在一个实施例中，第一粘合层207通过化学镀覆（electroless plating）来被形成在载体201和芯片焊盘205上。在其它实施例中，第一粘合层207可以通过使用诸如化学气相沉积、物理气相沉积或电镀之类的其它合适的工艺来被形成。
在实施例中，第一粘合层207可以被沉积在为约10nm至100nm的厚度中。在其它实施例中，第一粘合层207可以被沉积在为约50nm至100nm、60nm至90nm、70nm至80nm、20nm至90nm、30nm至80nm、40nm至70nm或50nm至60nm等的厚度中。
在一个实施例中，第一粘合层207在随后的处理期间可以完全扩散到位于下面的载体201中，并且可能不留在最后形成的芯片封装中。在另一个实施例中，第一粘合层207在随后的处理期间可以部分地扩散到位于下面的载体201中。
在图2C中，第二粘合层209被沉积在第一粘合层207上。第二粘合层209可以包括硅烷有机材料。
在实施例中，通过把硅烷有机材料的溶液涂敷到第一粘合层207上或者通过把第一粘合层207浸在硅烷有机材料的溶液中，第二粘合层209可以被形成在第一粘合层207上。在实施例中，硅烷有机层可以通过化学气相沉积或物理气相沉积来被涂敷，具有在原子单层直到100nm的范围内的厚度。
在图2D中，根据实施例，层压层211被沉积在第二粘合层209和芯片203上。在实施例中，包括涂树脂铜（RCC）材料的层压层211被形成。在实施里中，RCC材料的树脂可以包括由玻璃纤维填充的环氧树脂。在另一个实施例中，在芯片焊盘位置处具有对应的铜层切口的铜包覆层压层被形成为层压层211。层压层211可以被形成为具有为30μm至300μm的厚度。在其它实施例中，层压层211可以被形成为具有为约60μm至150μm、或80μm至110μm的厚度。层压层211可以通过真空层压或其它合适的工艺来被形成。
在图2D中，根据另一个实施例，密封层211被沉积在第二粘合层209和芯片203上。在实施例中，密封层211可以包括密封材料。密封材料可以包括来自下面的材料的组中的至少一个，所述组由以下组成：填充的或未填充的环氧化物、预浸渍复合纤维、加强的纤维、层压层、模材料、模化合物、热固材料、热塑材料、填充物颗粒、纤维加强的层压层、纤维加强的聚合物层压层、具有填充物颗粒的纤维加强的聚合物层压层。
在实施例中，密封层211可以通过球型封装（Glob Top）被沉积，其中密封材料被沉积在第二粘合层209和芯片203上，并且之后被固化。在另一个实施例中，密封层211可以通过利用围绕载体201的外围的坝的坝填充封装（Dam-and-Fill）来被沉积。
在图2E中，形成到所选择的芯片焊盘205和所选择的载体201区域的多个通孔213、215。通孔213、215延伸穿过层压层211、第一粘合层207和第二粘合层209，以接触所选择的载体201区域和所选择的芯片焊盘205。在实施例中，通孔213、215可以通过激光钻孔被形成。在另一个实施例中，通孔213、215可以通过机械钻孔或等离子体刻蚀或其它合适的工艺来被形成。
在图2F中，用导电材料（例如铜、银、锡、锡-铅等）来电镀地填充多个通孔213、215，以致实现到所选择的芯片焊盘和所选择的载体区域的电连接。在另一个实施例中，可以通过镀覆来用导电材料填充多个通孔213、215，使得通孔的内壁的表面被覆盖有导电材料。在实施例中，所形成的电连接从而可以被进一步形成结构或形成图形以实现想要的电路图形。
在如在图2F中所示的那样的实施例中，形成到源端子和栅端子的通孔213，并且形成到漏端子的通孔215。在其它实施例中，所形成的通孔213、215和电连接从而可以针对其它电路组件被形成。
图2F示出了根据实施例所形成的芯片嵌入封装。在另一个实施例中，根据图2A至2F的工艺最后所形成的芯片封装可以类似于图2F的芯片封装，但是没有第一粘合层207，因为第一粘合层207可以完全扩散到载体201中。
根据图1和图2A至2F的上面的实施例，层压层或密封层到载体的强粘合由具有锡或铟（例如纯锡或锡合金，例如锡-镍合金，例如纯铟或铟合金）的第一粘合层以及硅烷有机物的第二粘合层所实现。
在如在图3中所示的那样的图示的例子中，纯Sn层或Sn-Ni合金层207作为第一粘合层307被涂敷到被用作载体和芯片焊盘301的铜（Cu）衬底301上。第一粘合层307可以部分或完全扩散到铜衬底301中。粘合耦合硅烷有机层309被沉积在Si层或Sn-Ni合金层307上作为第二粘合层，所述第二粘合层在层压/密封工艺期间在金属Sn层或Sn-Ni合金层307与层压/密封层311之间形成化学接合。层压/密封层311可以包括树脂。通过优化浓度和处理，可以形成化学稳定的接合。
被包括在粘合耦合硅烷有机层309中的硅烷耦合剂可以拥有化学接合到树脂层压/密封层311的反应组以及化学结合到Sn层或Sn-Ni合金层307的反应组。一般，硅烷耦合剂具有结构X-Y-SiZ3，其中X是能够相互作用或者与聚合树脂（polymeric resin）反应的功能组，Y是有机键（linkage），而至少一个Z是能够与Sn层或Sn-Ni合金层307反应的反应的或可水解的组。在图3的例子中，X对应于R2而Y对应于R1，其中R1和R2可以是具有作为副原子（side-atom）的C、H、O、N、S或Si的碳链（C-）或Si-O链，Z对应于-OH。X组可以与聚合树脂接合，而SiZ3组可以接合到被部分或完全地扩散到金属衬底301中的Sn层或Sn-Ni合金层307。这通过有机组Y提供了从聚合树脂到金属衬底的化学链接（共价接合），从而改进聚合树脂到金属衬底的粘合。
可以被使用的被包括在硅烷有机层309中的硅烷耦合剂的例子可以包括但不限于y-氨基丙基三甲氧基硅烷（y-APS, y-aminopropyltrimethoxysilane）、y-环氧丙氧基丙基三甲氧基硅烷（y-GPS, y-glycidoxypropyltrimethoxysilane）、双三甲氧基甲硅烷基丙基氨基硅烷bistrimethoxysilylpropylaminosilane（BTSPA）和N-(3(氨乙基)Y-氨基丙基三甲氧基硅烷（N-(3(aminoethyl)Y-aminopropyltrimethoxysilane）。
在实施例中，其中Sn-Ni合金层被用作第一粘合层，Sn-Ni合金层的粗糙度可以被优化为使得纳米多孔区域（其最大/平均尺寸小于100nm）可以被生成，所述纳米多孔区域与不具有Sn-Ni合金粘合层的铜衬底相比具有增大的粘合力。
代替使用铜起纹理工艺，上面的实施例涂敷包括锡或铟层以及硅烷有机层的双层到载体和芯片焊盘金属化，作为载体与层压/密封层之间的稳定的粘合层。根据这些实施例，层压/密封到载体的强粘合借助于化学接合被实现。另外，实现了层压/密封到芯片正面处的源接触和栅接触的应力敏感位置的增加的粘合。此外，可以避免根据常规的方法的衬底/载体处理期间的芯片表面损坏和芯片粘合刻蚀。也可以实现芯片正面处的电镀地涂敷的铜焊盘厚度的节约。
图4示出了图示了根据另一个实施例的形成芯片封装的方法的流程图。
在401，至少一个芯片被附着在载体上。在实施例中，芯片可以被附着在引线框架上，其中引线框架可以被形成作为载体。
在403，芯片与载体之间的互连被形成。
在405，锡层被沉积在载体和互连上。
在实施例中，锡层还被沉积在载体下。
在407，密封层被沉积在锡层和芯片上。
图5A至5D图示了根据另一个实施例的用于形成芯片封装的工艺。
在图5A中，至少一个芯片503（只有一个芯片在该实施例中被示出）被附着在载体501上。芯片503可以通过使用焊料或环氧化物接合的管芯接合来被附着在载体501上。在实施例中，芯片503可以通过环氧化物接合或共晶接合（eutectic bonding）来被附着在载体501上。在实施例中，芯片503可以被附着在被形成为载体501的引线框架上。
在图5B中，例如通过导线接合来形成芯片503与载体501之间的互连505。在一些实施例中，可以通过热超声接合或激光结合通过使用焊料接合、铝导线接合、金导线接合或铜导线接合来形成互连505。
在图5C中，锡（Sn）层507被沉积在载体501和互连505上。锡层507可以包括纯锡。锡层507可以在一个例子中通过电解镀锡被沉积，或者在另一个例子中通过浸没（immersion）镀锡被沉积。在实施例中，锡层507可以被形成为具有为约2μm至4μm的厚度。在另一个实施例中，锡层507可以被形成为具有为约3μm的厚度。
在该实施例中，由于锡层507在管芯接合和导线接合之后被沉积，锡层507也被称为镀后（post-plate）锡层。
在实施例中，锡层507也可以被沉积在载体501下，例如用于制作载体501下的焊接焊盘。
在图5D中，密封层509被沉积在锡层507和芯片503上，从而形成根据实施例的芯片封装。在实施例中，密封层509可以通过压缩模塑（compression molding）、转移模塑（transfer molding）、注入模塑或其它合适的工艺来被沉积。
在实施例中，密封层509可以包括密封材料。密封材料可以包括来自下面的材料的组中的至少一个，所述组由以下组成：填充的或未填充的环氧化物、预浸渍（pre-impregnated）复合纤维、加强的纤维、层压层、模材料、模化合物、热固材料、热塑材料、填充物颗粒、纤维加强的层压层、纤维加强的聚合物层压层、具有填充物颗粒的纤维加强的聚合物层压层。
图6（a）示出了结构，其中芯片503被附着在载体501上，而互连505在沉积锡层之前被形成在芯片503与载体501之间。
图6（b）示出了结构，其中锡层507被沉积在图6（a）的载体501（例如载体501的传导部分）上，而锡层507被沉积在图6（a）的互连505上。
根据图4至6上面的实施例，在管芯接合和导线接合之后可以容易地镀覆锡层。到密封层的粘合可以由被镀覆在载体的传导部分和互连上的锡层所增强。
另外，由于形成可能包括例如模化合物的密封层中的模塑温度低于锡的熔化温度（232℃），锡层在模化合物层的沉积期间将不熔化。
图7示出了图示了根据另一实施例的形成芯片封装的方法的流程图。
在701，包括锡材料的粘合层被沉积在所选择的载体区域上。在实施例中，粘合层可以被沉积在所选择的引线框架区域上，其中引线框架可以被形成在载体上或者作为载体。
在实施例中，所选择的载体区域可以是芯片被附着到的区域或者互连将被形成的区域。通过例如镀覆或涂敷，粘合层被选择沉积在所选择的载体区域上。
在另一个实施例中，包括锡材料的粘合层也可以被沉积在载体下。
粘合层可以包括锡合金材料，或者可以包括与其它金属层一起的锡层。
在703，至少一个芯片被附着在被沉积在所选择的载体区域中的至少一个上的粘合层上。
在705，形成芯片与所选择的载体区域中的至少一个之间的互连。在实施例中，互连可以经由导线接合被形成。
在707，密封层被沉积在载体、粘合层和芯片上。
图8A至8C图示了根据一个实施例的用于形成芯片封装的工艺。
在图8A中，包括锡材料的粘合层803被沉积在所选择的载体801区域上。在实施例中，所选择的载体801区域可以是芯片被附着的区域或者互连将被形成的区域。
在一个实施例中，包括AgSn合金的粘合层803被选择性地镀覆在载体801上。在例子中，粘合层803可以包括20%的Ag和80%的Sn。在其它例子中，粘合层803可以包括提供想要的粘合强度的为其它合适的比例的Ag和Sn。在实施例中，粘合层803可以具有为至少2μm的厚度。
在另一个实施例中，粘合层803可以包括具有锡和金之间合适的比例的锡金（AuSn）合金，以致增强载体与密封层之间的粘合强度。在其它实施例中，粘合层803可以包括其它合适的锡合金，诸如锡铜合金、锡钯合金或锡镍合金。粘合层803可以被形成具有为最小2μm的厚度，以致保证之后到密封层的良好粘合。
在该实施例中，由于锡合金层803在管芯接合和导线接合之前被沉积，所以锡合金层803也被称为镀前（pre-plate）Sn合金层。
粘合层803在一个例子中可以通过电解镀覆被沉积，或者在另一个例子中可以通过浸没镀覆被沉积。
在另一个实施例中，粘合层803也可以被沉积在载体801下，例如以覆盖载体801的背面，例如用于在载体801下制作焊接焊盘。
在其它实施例中，粘合层803可以被镀覆在整个载体801上，而不要求选择性镀覆技术。
在图8B中，至少一个芯片805被附着在被沉积在所选择的载体801区域中的至少一个上的粘合层803上。芯片805可以通过管芯接合被附着在粘合层803上。在实施例中，芯片805可以通过环氧化物接合或共晶接合被附着在粘合层803上。
形成芯片805与所选择的载体区域中的至少一个之间的互连807。在实施例中，互连807可以经由导线接合被形成。在一些实施例中，可以通过热超声接合或激光结合通过使用焊料接合、铝导线接合、金导线接合或铜导线接合来形成互连807。
在图8C中，密封层809被沉积在载体801、粘合层803和芯片805上，从而形成根据实施例的芯片封装。密封层809可以通过压缩模塑、转移模塑、注入模塑或其它合适的工艺来被沉积。
在实施例中，密封层809可以包括密封材料。密封材料可以包括来自下面的材料的组中的至少一个，所述组由以下组成：填充的或未填充的环氧化物、预浸渍复合纤维、加强的纤维、层压层、模材料、热固材料、热塑材料、填充物颗粒、纤维加强的层压层、纤维加强的聚合物层压层、具有填充物颗粒的纤维加强的聚合物层压层。
根据实施例，在芯片接合和导线接合之前，AgSn合金被涂敷在载体的芯片接合面，并且也可以被涂敷在与芯片相对的载体的背面。AgSn（20/80）合金的高熔化温度（约350℃）能够实现共晶管芯接合和导线接合，而不引起所镀的AgSn合金熔化。传导的AgSn层具有对于管芯和导线可接合性的最小影响。该锡合金层可以增强对于密封层的粘合强度（由于AgSn合金的低的表面等电点（IEPS）），并且同时实现良好的可接合性。
图9A至9C图示了用于形成根据另一个实施例的芯片封装的工艺。
在图9A中，包括锡材料的粘合层903被沉积在所选择的载体901区域上。在实施例中，所选择的载体901区域可以是芯片将被附着到的区域，或者可以是互连将被形成的区域。在另一个实施例中，粘合层也可以被沉积在载体901下（未被示出），例如用于在载体901下制作焊接焊盘。
在一个实施例中，粘合层903可以是通过一层一层的选择性AgSnAg快速镀覆所形成的AgSnAg层。粘合层903的形成可以是在为约200℃的温度下为10分钟至30分钟的工艺。粘合层903可以包括被夹在第一银层905与第二银层909之间的锡层907。第一银层905可以防止载体材料（例如铜）到锡层907的扩散。锡夹层907可以增强粘合强度。第二银层909可以能够实现芯片与载体901之间的管芯接合以及导线接合。
在实施例中，锡层907可以具有为约2μm至3μm的厚度；第一银层905与载体901接触并且可以具有为约1μm至2μm的厚度；而第二银层909可以具有为约0.1μm至1μm的厚度。在另一个实施例中，第一银层905、锡层907与第二银层909的厚度可以分别为约2μm至4μm、2μm至4μm以及0.5μm至1μm。锡层907、第一银层905与第二银层909可以以其它合适的厚度被形成，以实现各自层的各自功能。
在该实施例中，由于AgSnAg层903在管芯接合和导线接合之前被沉积，AgSnAg层903也可以被称为镀前AgSnAg层。
在另一个实施例中，粘合层903可以包括被夹在第一银层905与第二有机涂层909（例如自组装单层）之间的锡层907。第一银层905可以具有为约2μm至4μm的厚度，而锡层907可以具有为约2μm至4μm的厚度。
在另一实施例中，粘合层903可以是多层结构，依次包括为约0.5 μm至1μm的Ni层、为约0.01μm至0.03 μm的Pd层、为约2μm至4μm的AgSn合金层（例如20%的Ag和80%的Sn）以及有机涂层（自组装单层）。在另一实施例中，粘合层903可以包括为约2μm至4μm的AgSn合金层（例如20%的Ag和80%的Sn）和有机涂层（自组装单层）。
在图9B中，至少一个芯片911被附着在被沉积在所选择的载体901区域的至少一个上的粘合层903上。芯片911可以通过管芯接合被附着在粘合层903上。在实施例中，芯片911可以通过环氧化物接合或共晶接合来被附着在粘合层903上。
形成芯片911与所选择的载体901区域中的至少一个之间的互连913。在实施例中，互连913可以经由导线接合来被形成。在一些实施例中，可以通过热超声接合或激光接合通过使用焊料接合、铝导线接合、金导线接合或铜导线接合来形成互连913。
在图9C中，密封层915被沉积在载体901、粘合层903和芯片911上，从而形成根据实施例的芯片封装。密封层915可以通过压缩模塑、转移模塑、注入模塑或其它合适的工艺来被沉积。
在实施例中，密封层915可以包括密封材料。密封材料可以包括来自下面的材料的组中的至少一个，所述组由以下组成：填充的或未填充的环氧化物、预浸渍复合纤维、加强的纤维、层压层、模材料、热固材料、热塑材料、填充物颗粒、纤维加强的层压层、纤维加强的聚合物层压层、具有填充物颗粒的纤维加强的聚合物层压层。
上面所述的各种实施例基于锡材料的低的表面等电点（IEPS），锡材料具有到密封（例如模化合物）的良好的粘合，并且增强模化合物上的粘合强度。IEPS是这样的PH，在其处，表面的电荷关于它的酸/碱以及电子施主-受主反应是中性的。
如在图10中所示，锡（Sn）与许多其它金属材料相比具有低的IEPS值。
因此，各种实施例通过电解镀覆在载体上引入包括锡或锡合金的层，从而增强对于模化合物的粘合强度。
虽然本发明已经参照特定的实施例被特别地示出和描述，但是本领域的技术人员应该理解的是，形式和细节的各种改变可以在那里被完成，而不离开如由所附权利要求所限定的那样的本发明的精神和范围。本发明的范围因而由所附权利要求所指示，并且因此意图包括与权利要求的等同物的意思和范围内的所有改变。

Claims (28)

1.一种形成芯片封装的方法，该方法包括：
在载体上附着至少一个芯片，该芯片包括与载体相对的芯片表面上的多个芯片焊盘；
在载体和芯片的芯片焊盘上沉积第一粘合层，该第一粘合层包括锡或铟；
在第一粘合层上沉积第二粘合层，该第二粘合层包括硅烷有机材料；以及
在第二粘合层和芯片上沉积层压层或密封层。
2.根据权利要求1所述的方法，其中，
在载体上附着至少一个芯片包括在引线框架上附着至少一个芯片。
3.根据权利要求1所述的方法，其中，
第一粘合层包括纯锡或锡合金，该锡合金包括锡以及一个或多个其它金属。
4.根据权利要求1所述的方法，其中，
第一粘合层包括锡镍合金、锡铅合金、锡银合金或锡铜合金。
5.根据权利要求1所述的方法，其中，
第一粘合层包括纯铟或铟合金，该铟合金包括铟以及一个或多个其它金属。
6.根据权利要求1所述的方法，进一步包括：
形成到所选择的芯片焊盘和所选择的载体区域的多个通孔，该通孔延伸穿过层压层或密封层、第一粘合层和第二粘合层。
7.根据权利要求1所述的方法，进一步包括：
通过激光钻孔来形成多个通孔。
8.根据权利要求6所述的方法，进一步包括：
用导电材料电镀地填充多个通孔。
9.根据权利要求1所述的方法，其中，
层压层包括涂树脂铜材料。
10.一种芯片封装，包括：
载体；
被附着在载体上的至少一个芯片，该芯片包括与载体相对的芯片表面上的多个芯片焊盘；
被部署在载体和芯片之上的层压层或密封层；
延伸穿过层压层或密封层到所选择的芯片焊盘和所选择的载体区域的多个通孔；以及
被形成在载体与层压层或密封层之间、以及芯片焊盘与层压层或密封层之间的粘合层，其中粘合层包括硅烷有机材料。
11.根据权利要求10所述的芯片封装，其中，
该载体包括引线框架。
12.一种形成芯片封装的方法，该方法包括：
在载体上附着至少一个芯片；
形成芯片与载体之间的互连；
在载体和互连上沉积锡层；
在锡层和芯片上沉积密封层;
其中形成芯片与载体之间的互连是通过形成延伸穿过芯片和载体的多个通孔来实现的。
13.根据权利要求12所述的方法，其中，
在载体上附着至少一个芯片包括在引线框架上附着至少一个芯片。
14.根据权利要求12所述的方法，进一步包括：
在载体下沉积锡层。
15.一种芯片封装，包括：
载体；
被附着在载体上的至少一个芯片；
芯片与载体之间的互连；
被沉积在载体和互连上的锡层；以及
被沉积在锡层和芯片上的密封层；
其中所述互连是通过形成延伸穿过芯片和载体的多个通孔来实现的。
16.根据权利要求15所述的芯片封装，其中，
载体包括引线框架。
17.一种形成芯片封装的方法，该方法包括：
在所选择的载体区域上沉积包括锡材料的粘合层；
在被沉积在所选择的载体区域中的至少一个上的粘合层上附着至少一个芯片；
形成芯片与所选择的载体区域中的至少一个之间的互连；以及
在载体、粘合层和芯片上沉积密封层；
其中所述形成互连是通过形成延伸穿过芯片和所选择的载体区域中的至少一个的多个通孔来实现的。
18.根据权利要求17所述的方法，其中，
在所选择的载体区域上沉积包括锡材料的粘合层包括在所选择的引线框架区域上沉积包括锡材料的粘合层。
19.根据权利要求17所述的方法，进一步包括：
在载体下沉积粘合层。
20.根据权利要求17所述的方法，其中，
粘合层包括锡银合金、锡金合金、锡铜合金、锡钯合金或锡镍合金。
21.根据权利要求20所述的方法，其中，
锡银合金包括80%的锡和20%的银。
22.根据权利要求20所述的方法，其中，
粘合层具有为至少2μm的厚度。
23.根据权利要求17所述的方法，其中，
粘合层包括被夹在第一银层与第二银层之间的锡层。
24.根据权利要求23所述的方法，其中，
锡层具有为2μm至3μm的厚度；
第一银层具有为1μm至2μm的厚度，第一银层与载体接触；
第二银层具有为0.1μm至1μm的厚度。
25.根据权利要求17所述的方法，其中，
粘合层包括被夹在银层与有机涂层之间的锡层；或者
粘合层包括镍层、钯层、锡银合金层和有机涂层的序列；或者
粘合层包括锡银合金层和有机涂层。
26.根据权利要求17所述的方法，进一步包括：
在载体下面沉积粘合层。
27.一种芯片封装，包括：
载体；
包括锡材料并且被沉积在所选择的载体区域上的粘合层；
被附着在被沉积在所选择的载体区域中的至少一个上的粘合层上的至少一个芯片；
被形成在芯片与所选择的载体区域中的至少一个之间的互连；以及
被沉积在载体、粘合层和芯片上的密封层；
其中所述互连是通过形成延伸穿过芯片和载体的多个通孔来实现的。
28.根据权利要求27所述的芯片封装，其中，
载体包括引线框架。
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