DE112013005987B4 - Halbleitervorrichtung mit nichtflüchtiger Speicherzelle und Verfahren zur Herstellung - Google Patents

Halbleitervorrichtung mit nichtflüchtiger Speicherzelle und Verfahren zur Herstellung Download PDF

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Publication number
DE112013005987B4
DE112013005987B4 DE112013005987.8T DE112013005987T DE112013005987B4 DE 112013005987 B4 DE112013005987 B4 DE 112013005987B4 DE 112013005987 T DE112013005987 T DE 112013005987T DE 112013005987 B4 DE112013005987 B4 DE 112013005987B4
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gate
region
dielectric
layer
semiconductor device
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German (de)
English (en)
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DE112013005987T5 (de
Inventor
Kuo Tung CHANG
Chun Chen
Shenqing Fang
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Infineon Technologies LLC
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Spansion LLC
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
DE112013005987.8T 2012-12-14 2013-12-05 Halbleitervorrichtung mit nichtflüchtiger Speicherzelle und Verfahren zur Herstellung Active DE112013005987B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/715,565 2012-12-14
US13/715,565 US8836006B2 (en) 2012-12-14 2012-12-14 Integrated circuits with non-volatile memory and methods for manufacture
PCT/US2013/073327 WO2014093126A1 (en) 2012-12-14 2013-12-05 Integrated circuits with non-volatile memory and methods for manufacture

Publications (2)

Publication Number Publication Date
DE112013005987T5 DE112013005987T5 (de) 2015-09-10
DE112013005987B4 true DE112013005987B4 (de) 2021-02-04

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Country Status (4)

Country Link
US (3) US8836006B2 (https=)
JP (1) JP6461003B2 (https=)
DE (1) DE112013005987B4 (https=)
WO (1) WO2014093126A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8836006B2 (en) 2012-12-14 2014-09-16 Spansion Llc Integrated circuits with non-volatile memory and methods for manufacture
US9368644B2 (en) * 2013-12-20 2016-06-14 Cypress Semiconductor Corporation Gate formation memory by planarization
US20150200279A1 (en) * 2014-01-12 2015-07-16 United Microelectronics Corp. Method of manufacturing memory cell
US9406687B1 (en) * 2015-03-23 2016-08-02 Globalfoundries Singapore Pte. Ltd. Integration of memory devices with different voltages
KR20170131787A (ko) * 2016-05-20 2017-11-30 삼성디스플레이 주식회사 박막트랜지스터의 제조방법 및 박막트랜지스터를 채용하는 표시장치
FR3078792B1 (fr) * 2018-03-07 2020-03-27 Stmicroelectronics (Rousset) Sas Circuit integre muni de leurres contre l'ingenierie inverse et procede de fabrication correspondant

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100059810A1 (en) * 2008-09-08 2010-03-11 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
JP2010205791A (ja) * 2009-02-27 2010-09-16 Renesas Electronics Corp 半導体装置およびその製造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844839A (en) * 1995-07-19 1998-12-01 Texas Instruments Incorporated Programmable and convertible non-volatile memory array
US5824584A (en) 1997-06-16 1998-10-20 Motorola, Inc. Method of making and accessing split gate memory device
US5969383A (en) 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
TW546840B (en) 2001-07-27 2003-08-11 Hitachi Ltd Non-volatile semiconductor memory device
JP4647175B2 (ja) * 2002-04-18 2011-03-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP4601287B2 (ja) 2002-12-26 2010-12-22 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
JP4746835B2 (ja) 2003-10-20 2011-08-10 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
JP4546117B2 (ja) 2004-03-10 2010-09-15 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
JP5007017B2 (ja) 2004-06-30 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2006041354A (ja) 2004-07-29 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
US7425482B2 (en) * 2004-10-13 2008-09-16 Magna-Chip Semiconductor, Ltd. Non-volatile memory device and method for fabricating the same
JP5116987B2 (ja) 2005-05-23 2013-01-09 ルネサスエレクトロニクス株式会社 集積半導体不揮発性記憶装置
JP4659527B2 (ja) 2005-06-20 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2007194511A (ja) 2006-01-23 2007-08-02 Renesas Technology Corp 不揮発性半導体記憶装置およびその製造方法
JP4928825B2 (ja) 2006-05-10 2012-05-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5149539B2 (ja) 2007-05-21 2013-02-20 ルネサスエレクトロニクス株式会社 半導体装置
US7795091B2 (en) 2008-04-30 2010-09-14 Winstead Brian A Method of forming a split gate memory device and apparatus
US7902022B2 (en) 2008-07-29 2011-03-08 Freescale Semiconductor, Inc. Self-aligned in-laid split gate memory and method of making
JP5538828B2 (ja) * 2009-11-11 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2011181124A (ja) 2010-02-26 2011-09-15 Renesas Electronics Corp 不揮発性半導体記憶装置および不揮発性半導体記憶装置の動作方法
JP2012023269A (ja) * 2010-07-16 2012-02-02 Renesas Electronics Corp 不揮発性記憶装置およびその製造方法
JP2011014920A (ja) 2010-08-30 2011-01-20 Renesas Electronics Corp 不揮発性半導体記憶装置
JP2012114269A (ja) * 2010-11-25 2012-06-14 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US8564044B2 (en) * 2011-03-31 2013-10-22 Freescale Semiconductor, Inc. Non-volatile memory and logic circuit process integration
US9111865B2 (en) * 2012-10-26 2015-08-18 Freescale Semiconductor, Inc. Method of making a logic transistor and a non-volatile memory (NVM) cell
US8836006B2 (en) 2012-12-14 2014-09-16 Spansion Llc Integrated circuits with non-volatile memory and methods for manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100059810A1 (en) * 2008-09-08 2010-03-11 Renesas Technology Corp. Semiconductor device and a method of manufacturing the same
JP2010205791A (ja) * 2009-02-27 2010-09-16 Renesas Electronics Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US20150031197A1 (en) 2015-01-29
US20160218113A1 (en) 2016-07-28
US20140167139A1 (en) 2014-06-19
DE112013005987T5 (de) 2015-09-10
WO2014093126A1 (en) 2014-06-19
JP6461003B2 (ja) 2019-01-30
US8836006B2 (en) 2014-09-16
JP2016503960A (ja) 2016-02-08
US9368588B2 (en) 2016-06-14

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