DE10297582T5 - Halbleiterbauteil mit einer dünnen Oxidbeschichtung und ein Verfahren zur Herstellung desselben - Google Patents
Halbleiterbauteil mit einer dünnen Oxidbeschichtung und ein Verfahren zur Herstellung desselben Download PDFInfo
- Publication number
- DE10297582T5 DE10297582T5 DE10297582T DE10297582T DE10297582T5 DE 10297582 T5 DE10297582 T5 DE 10297582T5 DE 10297582 T DE10297582 T DE 10297582T DE 10297582 T DE10297582 T DE 10297582T DE 10297582 T5 DE10297582 T5 DE 10297582T5
- Authority
- DE
- Germany
- Prior art keywords
- oxide coating
- substrate
- gate electrode
- etching
- nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 239000011248 coating agent Substances 0.000 title claims abstract description 48
- 238000000576 coating method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 125000006850 spacer group Chemical group 0.000 claims abstract description 29
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 28
- 239000002019 doping agent Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 25
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 4
- 230000000717 retained effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006735 deficit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2103701A | 2001-12-19 | 2001-12-19 | |
| US10/021,037 | 2001-12-19 | ||
| PCT/US2002/041103 WO2003054951A1 (en) | 2001-12-19 | 2002-12-19 | Semiconductor device comprising a thin oxide liner and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE10297582T5 true DE10297582T5 (de) | 2004-11-11 |
Family
ID=21801954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE10297582T Ceased DE10297582T5 (de) | 2001-12-19 | 2002-12-19 | Halbleiterbauteil mit einer dünnen Oxidbeschichtung und ein Verfahren zur Herstellung desselben |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2005517285A (enExample) |
| KR (1) | KR20040068269A (enExample) |
| CN (1) | CN1322565C (enExample) |
| AU (1) | AU2002358269A1 (enExample) |
| DE (1) | DE10297582T5 (enExample) |
| GB (1) | GB2399222B (enExample) |
| WO (1) | WO2003054951A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583016B1 (en) * | 2002-03-26 | 2003-06-24 | Advanced Micro Devices, Inc. | Doped spacer liner for improved transistor performance |
| JP2008124441A (ja) * | 2006-10-19 | 2008-05-29 | Tokyo Electron Ltd | 半導体装置の製造方法 |
| DE102011005641B4 (de) * | 2011-03-16 | 2018-01-04 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Leistungssteigerung in Transistoren durch Reduzierung der Absenkung aktiver Gebiete und durch Entfernen von Abstandshaltern |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868617A (en) * | 1988-04-25 | 1989-09-19 | Elite Semiconductor & Sytems International, Inc. | Gate controllable lightly doped drain mosfet devices |
| US5714413A (en) * | 1995-12-11 | 1998-02-03 | Intel Corporation | Method of making a transistor having a deposited dual-layer spacer structure |
| US6472281B2 (en) * | 1998-02-03 | 2002-10-29 | Matsushita Electronics Corporation | Method for fabricating semiconductor device using a CVD insulator film |
| US6162692A (en) * | 1998-06-26 | 2000-12-19 | Advanced Micro Devices, Inc. | Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor |
| US6251764B1 (en) * | 1999-11-15 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to form an L-shaped silicon nitride sidewall spacer |
| US6294480B1 (en) * | 1999-11-19 | 2001-09-25 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an L-shaped spacer with a disposable organic top coating |
| US6156598A (en) * | 1999-12-13 | 2000-12-05 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a lightly doped source and drain structure using an L-shaped spacer |
| US6277700B1 (en) * | 2000-01-11 | 2001-08-21 | Chartered Semiconductor Manufacturing Ltd. | High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness |
-
2002
- 2002-12-19 GB GB0412884A patent/GB2399222B/en not_active Expired - Lifetime
- 2002-12-19 JP JP2003555574A patent/JP2005517285A/ja active Pending
- 2002-12-19 AU AU2002358269A patent/AU2002358269A1/en not_active Abandoned
- 2002-12-19 DE DE10297582T patent/DE10297582T5/de not_active Ceased
- 2002-12-19 CN CNB028257502A patent/CN1322565C/zh not_active Expired - Fee Related
- 2002-12-19 WO PCT/US2002/041103 patent/WO2003054951A1/en not_active Ceased
- 2002-12-19 KR KR10-2004-7009490A patent/KR20040068269A/ko not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040068269A (ko) | 2004-07-30 |
| CN1322565C (zh) | 2007-06-20 |
| JP2005517285A (ja) | 2005-06-09 |
| GB0412884D0 (en) | 2004-07-14 |
| GB2399222A (en) | 2004-09-08 |
| GB2399222B (en) | 2005-07-20 |
| CN1606801A (zh) | 2005-04-13 |
| WO2003054951A1 (en) | 2003-07-03 |
| AU2002358269A1 (en) | 2003-07-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| 8131 | Rejection |