JP2005517285A - 薄い酸化物ライナーを含む半導体デバイスおよびその製造方法 - Google Patents

薄い酸化物ライナーを含む半導体デバイスおよびその製造方法 Download PDF

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Publication number
JP2005517285A
JP2005517285A JP2003555574A JP2003555574A JP2005517285A JP 2005517285 A JP2005517285 A JP 2005517285A JP 2003555574 A JP2003555574 A JP 2003555574A JP 2003555574 A JP2003555574 A JP 2003555574A JP 2005517285 A JP2005517285 A JP 2005517285A
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JP
Japan
Prior art keywords
oxide liner
substrate
gate electrode
oxide
liner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003555574A
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English (en)
Japanese (ja)
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JP2005517285A5 (enExample
Inventor
ルーニング スコット
カドシュ ダニエル
ディー． チーク ジョン
エフ． ビュラー ジェイムズ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2005517285A publication Critical patent/JP2005517285A/ja
Publication of JP2005517285A5 publication Critical patent/JP2005517285A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2003555574A 2001-12-19 2002-12-19 薄い酸化物ライナーを含む半導体デバイスおよびその製造方法 Pending JP2005517285A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2103701A 2001-12-19 2001-12-19
PCT/US2002/041103 WO2003054951A1 (en) 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JP2005517285A true JP2005517285A (ja) 2005-06-09
JP2005517285A5 JP2005517285A5 (enExample) 2006-02-02

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ID=21801954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003555574A Pending JP2005517285A (ja) 2001-12-19 2002-12-19 薄い酸化物ライナーを含む半導体デバイスおよびその製造方法

Country Status (7)

Country Link
JP (1) JP2005517285A (enExample)
KR (1) KR20040068269A (enExample)
CN (1) CN1322565C (enExample)
AU (1) AU2002358269A1 (enExample)
DE (1) DE10297582T5 (enExample)
GB (1) GB2399222B (enExample)
WO (1) WO2003054951A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005522033A (ja) * 2002-03-26 2005-07-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ソース／ドレイン拡張部からドーパントが外方拡散しないようにするための、シリコン酸化物ライナーのイオン注入
WO2008047635A1 (fr) * 2006-10-19 2008-04-24 Tokyo Electron Limited Procédé de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011005641B4 (de) * 2011-03-16 2018-01-04 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Leistungssteigerung in Transistoren durch Reduzierung der Absenkung aktiver Gebiete und durch Entfernen von Abstandshaltern

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868617A (en) * 1988-04-25 1989-09-19 Elite Semiconductor & Sytems International, Inc. Gate controllable lightly doped drain mosfet devices
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US6472281B2 (en) * 1998-02-03 2002-10-29 Matsushita Electronics Corporation Method for fabricating semiconductor device using a CVD insulator film
US6162692A (en) * 1998-06-26 2000-12-19 Advanced Micro Devices, Inc. Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor
US6251764B1 (en) * 1999-11-15 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form an L-shaped silicon nitride sidewall spacer
US6294480B1 (en) * 1999-11-19 2001-09-25 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer with a disposable organic top coating
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6277700B1 (en) * 2000-01-11 2001-08-21 Chartered Semiconductor Manufacturing Ltd. High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005522033A (ja) * 2002-03-26 2005-07-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ソース／ドレイン拡張部からドーパントが外方拡散しないようにするための、シリコン酸化物ライナーのイオン注入
WO2008047635A1 (fr) * 2006-10-19 2008-04-24 Tokyo Electron Limited Procédé de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur

Also Published As

Publication number Publication date
GB2399222A (en) 2004-09-08
CN1322565C (zh) 2007-06-20
DE10297582T5 (de) 2004-11-11
KR20040068269A (ko) 2004-07-30
GB0412884D0 (en) 2004-07-14
CN1606801A (zh) 2005-04-13
AU2002358269A1 (en) 2003-07-09
GB2399222B (en) 2005-07-20
WO2003054951A1 (en) 2003-07-03

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