Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
  • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
  • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
  • H01L21/2652—Through-implantation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

Definitions

• the present invention relates to the field of semiconductor devices, and more particularly, to the formation of doped regions in a semiconductor device.
• a conventional process for preparing such a semiconductor device involves the deposition of a polysilicon gate layer over silicon substrate.
• the polysilicon gate layer is then etched to a desired width. The etching is performed anisotropically to provide substantially vertical sidewalls on the gate electrode.
• a source/drain extension implant is typically performed.
• the polysilicon gate electrode masks the substrate directly underneath the electrode, so that source/drain extensions are formed adjacent to the gate electrode.
• sidewall spacers are formed on the gate electrode.
• a deep source/drain implant process is then performed to create the source/drain regions.
• the sidewall spacers formed on the gate electrode act as masks to prevent the deep source/drain implants from being implanted into the substrate directly underneath the sidewall spacers. By this process, the deep source/drain regions are separated from the gate electrode by the width of the spacers.
• an annealing step activates the implanted dopants.
• the sidewall spacers are typically formed on the sidewalls on the gate electrode by etching of a dielectric layer such as silicon nitride that has been deposited over the substrate and the gate electrode. It is known to employ a liner oxide deposited prior to the primary dielectric layer to use as an etch stop layer during the etching of the silicon nitride sidewall spacers. The anisotropic etching of the dielectric layer etches the silicon nitride and stops on the liner oxide, preventing undesirable gouging of the silicon substrate.
• the liner oxide is typically deposited with a thickness of between 100 A to 30 ⁇ A, and most typically, 150 A.
• a semiconductor device fabricated with this methodology is depicted in Figure 1.
• the semiconductor device includes a substrate 10, gate electrode 12, liner oxide 14, silicon nitride spacer 16, source/drain extensions 18 and deep source/drain regions 20.
• a concern recognized by the inventors of such a configuration and methodology relates to the out-diffusion of dopants, especially from the source/drain extensions 18, into overlayers of the semiconductor device.
• the out-diffusion of the dopants results in higher resistance source/drains and more graded junctions. Both of these problems degrade the transistor performance.
• an etch stop layer to prevent gouging during the spacer etch, but that will not serve as a dopant sink for out-diffusion of dopants during thermal processing.
• embodiments of the present invention which provide a method of forming a semiconductor device, comprising the steps of forming a gate electrode on a substrate, and forming an oxide liner less than 100 A in thickness on the substrate and the gate electrode.
• a nitride layer is deposited on the oxide liner, and the nitride layer is etched to form nitride spacers, this etching stopping on the oxide liner.
• oxide liner that is less than 100 A in thickness suppresses out-diffusion of the dopants since that layer forms less of a sink for dopants and more dopants are retained in the substrate.
• oxide liner In order to allow the oxide liner to still serve the function of etch stopping during the etching of the nitride layer, a very selective dry etch may be used, using CF 4 chemistries during the spacer formation, in certain preferred embodiments of the invention.
• embodiments of the present invention which provide a semiconductor device, comprising a substrate, a gate electrode on the substrate, and an oxide liner on the substrate.
• the oxide liner has a thickness of less than 100 A.
• Nitride sidewall spacers are provided on the oxide liner.
• Figure 1 is a schematic, cross-sectional view of a semiconductor device constructed in accordance with prior art methodologies, illustrating the out-diffusion of dopants into overlayers.
• Figure 2 depicts a semiconductor device manufactured in accordance with embodiments of the present invention, during one stage of manufacture.
• Figure 3 depicts the structure of Figure 2, following the formation of an oxide liner in accordance with embodiments of the present invention.
• Figure 4 shows the structure of Figure 3, after source/drain extension implants are performed, in accordance with embodiments of the present invention.
• Figure 5 depicts the structure of Figure 4, after a dielectric layer has been deposited, in accordance with embodiments of the present invention.
• Figure 6 shows the structure of Figure 5, following the etching of the dielectric layer to form sidewall spacers on the gate electrode, in accordance with embodiments of the present invention.
• Figure 7 depicts the structure of Figure 6, after a deep source/drain implant has been performed to create source/drain regions of the semiconductor device, in accordance with embodiments of the present invention.
• FIGS. 8a-8c depict the formation of a disposable spacer and an implant process employing the disposable spacer in accordance with embodiments of the invention.
• the present invention addresses and solves problems related to the out-diffusion of dopants into overlayers during thermal processing, resulting in higher resistance source/drain regions and more graded junctions, decreasing transistor perfonnance.
• the present invention solves these problems, in part, by forming a semiconductor device with an oxide liner that is less than 100 A in thickness on a substrate and a gate electrode. A nitride layer formed on the oxide liner is etched to form nitride spacers, this etching stopping on the oxide liner.
• FIG. 2 shows the structure of a semiconductor device during one step of manufacturing.
• a gate electrode 32 made up of polysilicon, for example, is formed on a substrate 30.
• the formation of the polysilicon gate electrode 32, or metal gate electrode, for example, is accomplished in a conventional manner, such as by deposition of a polysilicon gate layer over a silicon substrate, followed by photolithography and etching steps.
• a gate oxide (not shown) may also be provided between the substrate 30 and the polysilicon gate electrode 32, to create a gate dielectric.
• an oxide liner 34 is deposited.
• a typical method of forming an oxide liner is through PECVD (plasma enhanced chemical vapor deposition) methods which are known to those of ordinary skill in the art.
• the oxide liner is deposited to a thickness of less than 100 A, and between 20 and 70 A in especially preferred embodiments. In even further especially preferred embodiments, the thickness of the oxide liner is less than about 45 A thick.
• the oxide liner 34 covers the gate electrode 32 and the surface of the substrate 30.
• a source/drain extension implant is performed in a conventional manner to create source/drain extensions 36 adjacent to the gate electrode 32.
• the gate electrode 32 masks the substrate 30 to prevent implantation of dopants directly underneath the gate electrode 32.
• Figures 3 and 4 depict one embodiment of the sequence of process steps in the present invention, in other embodiments, the steps of Figures 3 and 4 are reversed, so that the extension implant is performed prior to the deposition of the oxide liner 34.
• a dielectric layer such as silicon nitride, for example, is deposited as a layer 38 over the oxide liner 34.
• the dielectric layer 38 may be deposited in a conventional manner, such as by CVD.
• Other materials may be used in the dielectric layer 38, provided such materials may be etched very selectively in comparison to oxide.
• the silicon nitride in the dielectric layer 38 has been etched to form sidewall spacers 40. It is critical for the oxide liner 34 to act as an etch stop to prevent gouging of the silicon substrate 30 during the nitride etch. Since the oxide liner 34 has been made thinner than in conventional prior art methods, care must be taken to avoid overetching. Accordingly, a highly selective dry etch is employed to form the sidewall spacers 40.
• the etch chemistry must exhibit high nitride-to-oxide selectivity so that the thin liner will serve as an adequate etch stop layer.
• An exemplary chemistry includes CF 4 .
• Other etchant chemistries and recipes for etching, including plasma etching or reactive ion etching include the following: CF 4 /HBr/He0 2 and Cl 2 /HBr ⁇ e0 2 .
• Figure 7 shows the structure of Figure 6 following the formation of source/drain regions 42 by a deep implant process and subsequent thermal processing.
• the sidewalls spacers 40 act as masks to prevent implantation of dopants in the substrate 30 directly underneath the sidewall spacers 40.
• Conventional dosages, implantation energies, and thermal annealing parameters may be employed.
• the thin oxide liner 34 suppresses the out-diffusion of the dopants in the source/drain extensions 36 and the source/drain regions 42, since the thinness of the oxide liner 34 substantially prevents the liner from acting as a sink for dopants. Hence, more dopants are retained in the substrate 30. The overall affect of this is to lower the resistance of the source/drain regions 42 and the source/drain extensions 36, and produce less graded junctions. This acts to improve the transistor performance.
• germanium oxide is employed as a disposable spacer material.
• Germanium oxide is preferred as it has the property of dissolving in water.
• the germanium oxide may be deposited by a sputter method, or by Ge CVD with subsequent oxidation. It is then anisotropically dry etched to form a spacer.
• Figure 8a depicts an arrangement after germanium oxide spacers 50 have been deposited over a liner 52, made of oxide, nitride, or other material.
• Disposable spacers may be used in different manners.
• An exemplary use is to perform deep source/drain implants 54 after the formation of the spacers, as depicted in Figure 8b.
• An anneal step is then performed that may be hotter than conventional, since the source/drain extension formed after spacer removal will not be subjected to the higher temperatures.
• the spacers 50 are then disposed of and an LDD implant 56 and lower temperature anneal is performed, as indicated in Figure 8c.
• the germanium oxide is advantageous in that it can be removed very safely in water, and very selectively from other films traditionally used in semiconductor processing.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• High Energy & Nuclear Physics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Toxicology (AREA)
• Health & Medical Sciences (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Formation Of Insulating Films (AREA)
• Electrodes Of Semiconductors (AREA)

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• 2002
  • 2002-12-19 GB GB0412884A patent/GB2399222B/en not_active Expired - Lifetime
  • 2002-12-19 JP JP2003555574A patent/JP2005517285A/ja active Pending
  • 2002-12-19 AU AU2002358269A patent/AU2002358269A1/en not_active Abandoned
  • 2002-12-19 DE DE10297582T patent/DE10297582T5/de not_active Ceased
  • 2002-12-19 CN CNB028257502A patent/CN1322565C/zh not_active Expired - Fee Related
  • 2002-12-19 WO PCT/US2002/041103 patent/WO2003054951A1/en not_active Ceased
  • 2002-12-19 KR KR10-2004-7009490A patent/KR20040068269A/ko not_active Ceased

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