GB0412884D0 - Semiconductor device comprising a thin oxide liner and method of manufacturing the same - Google Patents

Semiconductor device comprising a thin oxide liner and method of manufacturing the same

Info

Publication number
GB0412884D0
GB0412884D0 GBGB0412884.9A GB0412884A GB0412884D0 GB 0412884 D0 GB0412884 D0 GB 0412884D0 GB 0412884 A GB0412884 A GB 0412884A GB 0412884 D0 GB0412884 D0 GB 0412884D0
Authority
GB
United Kingdom
Prior art keywords
manufacturing
semiconductor device
same
thin oxide
oxide liner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB0412884.9A
Other versions
GB2399222A (en
GB2399222B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0412884D0 publication Critical patent/GB0412884D0/en
Publication of GB2399222A publication Critical patent/GB2399222A/en
Application granted granted Critical
Publication of GB2399222B publication Critical patent/GB2399222B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652Through-implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
GB0412884A 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same Expired - Lifetime GB2399222B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2103701A 2001-12-19 2001-12-19
PCT/US2002/041103 WO2003054951A1 (en) 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same

Publications (3)

Publication Number Publication Date
GB0412884D0 true GB0412884D0 (en) 2004-07-14
GB2399222A GB2399222A (en) 2004-09-08
GB2399222B GB2399222B (en) 2005-07-20

Family

ID=21801954

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0412884A Expired - Lifetime GB2399222B (en) 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same

Country Status (7)

Country Link
JP (1) JP2005517285A (en)
KR (1) KR20040068269A (en)
CN (1) CN1322565C (en)
AU (1) AU2002358269A1 (en)
DE (1) DE10297582T5 (en)
GB (1) GB2399222B (en)
WO (1) WO2003054951A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583016B1 (en) * 2002-03-26 2003-06-24 Advanced Micro Devices, Inc. Doped spacer liner for improved transistor performance
JP2008124441A (en) * 2006-10-19 2008-05-29 Tokyo Electron Ltd Manufacturing method of semiconductor device
DE102011005641B4 (en) * 2011-03-16 2018-01-04 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG A method of increasing performance in transistors by reducing subsidence of active regions and by removing spacers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868617A (en) * 1988-04-25 1989-09-19 Elite Semiconductor & Sytems International, Inc. Gate controllable lightly doped drain mosfet devices
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US6472281B2 (en) * 1998-02-03 2002-10-29 Matsushita Electronics Corporation Method for fabricating semiconductor device using a CVD insulator film
US6162692A (en) * 1998-06-26 2000-12-19 Advanced Micro Devices, Inc. Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor
US6251764B1 (en) * 1999-11-15 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form an L-shaped silicon nitride sidewall spacer
US6294480B1 (en) * 1999-11-19 2001-09-25 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer with a disposable organic top coating
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6277700B1 (en) * 2000-01-11 2001-08-21 Chartered Semiconductor Manufacturing Ltd. High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness

Also Published As

Publication number Publication date
WO2003054951A1 (en) 2003-07-03
GB2399222A (en) 2004-09-08
CN1606801A (en) 2005-04-13
DE10297582T5 (en) 2004-11-11
JP2005517285A (en) 2005-06-09
AU2002358269A1 (en) 2003-07-09
CN1322565C (en) 2007-06-20
GB2399222B (en) 2005-07-20
KR20040068269A (en) 2004-07-30

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