CN1606801A - Semiconductor device comprising a thin oxide liner and method of manufacturing the same - Google Patents
Semiconductor device comprising a thin oxide liner and method of manufacturing the same Download PDFInfo
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- CN1606801A CN1606801A CNA028257502A CN02825750A CN1606801A CN 1606801 A CN1606801 A CN 1606801A CN A028257502 A CNA028257502 A CN A028257502A CN 02825750 A CN02825750 A CN 02825750A CN 1606801 A CN1606801 A CN 1606801A
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- oxide liner
- base material
- grid
- etching
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 34
- 229910045601 alloy Inorganic materials 0.000 claims description 24
- 239000000956 alloy Substances 0.000 claims description 24
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 10
- 239000007943 implant Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000002019 doping agent Substances 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 5
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000032696 parturition Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 101100400452 Caenorhabditis elegans map-2 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003325 tomography Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
A method of forming a semiconductor device provides a gate electrode (32) on a substrate (30); and an oxide liner (34) that is less than 100 A in thickness on the substrate (30) and the gate electrode (32). A nitride layer (38) is formed on the oxide liner (34). The nitride layer (38) is etched to form nitride spacers (40), the etching stopping on the oxide liner (34). The thinner oxide liner (34), e.g., less than 100 A, prevents the liner (34) from acting as a sink for dopants during thermal processing so that the dopants in the source/drain extension regions (36) and the source/drain regions (42) remain in the substrate (30) during the thermal processing, thereby preventing degradation of transistor performance.
Description
Technical field
The present invention relates to a kind of field of semiconductor devices, more detailed it, relate to a kind of structure of semiconductor device doped region.
Background technology
Nearly recent decades, the application of semiconductor industry by semiconductor technology used and produced the high electronic installation of the little integrated level of volume to live through major transformation, and recently common semiconductor technology many be material with silicon.Knownly be included in deposit spathic silicon grid layer on the silicon substrate in order to the program for preparing this kind semiconductor device.Then this polysilicon of etching is to required width.This etching is to carry out to form the sidewall of approximate vertical on grid in the mode of anisotropic.
After this grid forms, then carry out the implantation that source/drain extends usually.This polysilicon gate directly is covered on the base material under this electrode, and in view of the above, it is to be adjacent to this lock electricity promptly to be formed that source/drain extends.
After this source/drain extends implantation, then form sidewall spacers on this grid.Then go deep into the source/drain implant procedure to generate this regions and source by execution.The sidewall spacers that is formed on this grid is to go deep into source/drain and implant in the base material that directly is implanted under this sidewall spacers in order to prevent this as shielding.By this program, this gos deep into regions and source and can be separated by this interval and this grid.After this implant procedure is finished, activate the alloy of being implanted by annealing steps.
The etching that this sidewall spacers is typically by dielectric layer is formed on this gate lateral wall, and this dielectric layer can be for example for being deposited on the silicon nitride on this base material and the grid.Known is to be used in to deposit liner oxide as the etch stop layer in this silicon nitride sidewall spacers etching process before this main dielectric layer forms.The non-of this dielectric layer waits the phasic property etching to be this silicon nitride of etching and to end on this liner oxide, uses preventing that this silicon substrate is destroyed improperly.This liner oxide is deposited to the thickness between about 100 dust to 300 dusts usually, is typically the thickness that is deposited into 150 dusts.Semiconductor device by aforesaid technology manufacturing is to be exposed among Fig. 1.This semiconductor device comprises base material 10, grid 12, liner oxide 14, silicon nitride spacer 16, source/drain extension 18 and gos deep into regions and source 20.
The inventor thinks and can produce and the relevant problem of alloy outdiffusion (out-diffusion) by aforesaid structure or method, particularly extends 18 more obvious to the cover layer of this semiconductor device from source/drain.The connection that the outdiffusion of this alloy causes the source/drain of living high electrical resistance and more tilts.Aforesaid two problems all can reduce this transistorized usefulness.The oxide layer 14 that is used as the etch stop layer in this silicon nitride sidewall spacers etching process is as the usefulness of alloy groove in follow-up heat treatment process.In view of the above, can make this alloy extend 18 outdiffusions to this oxide liner 14 from this source/drain.Therefore, though etch stop layer can prevent the generation of tomography in the spaced etch process, can not be as the doping groove of alloy outdiffusion in heat treatment process.
Summary of the invention
Therefore need a kind ofly prevent that the alloy outdiffusion is to cover layer but provide the etch-stop function to use to carry out etched semiconductor device structure of sidewall spacers and method for making under the situation of not destroying this silicon substrate.
For solving aforementioned and other problem embodiments of the invention provide a kind of method that forms semiconductor device, be included in and form grid on the base material, and on this base material and grid, form the oxide liner of thickness less than 100 dusts.Nitride layer is on this oxide liner, and this nitride layer of etching to be to form nitride spacers, and this etching is to end on this oxide liner.
This thickness is in order to prevent because of this layer shortcoming alloy groove so more alloy is retained in the generation that causes the alloy diffusion in the base material less than the oxide liner of 100 dusts.For make the sustainable function that etch-stop is provided of this oxide liner in the nitride layer etching process, can utilize specific dry-etching, in part preferred embodiment of the present invention, in the forming process of interval, can utilize tetrafluoromethane (CF
4) chemical action carries out dry-etching.Preventing of alloy outdiffusion particularly the preventing of the alloy outdiffusion of source/drain elongated area, with causing the connection of giving birth to more low-resistance source/drain and more not tilting, used the lifting performance of transistors.
Aforesaid problem can be solved by the semiconductor device that is provided in the embodiments of the invention again, and this semiconductor device comprises base material, in grid on this base material and the oxide liner on this base material.This oxide liner has the thickness of about 100 dusts.Nitride sidewall spacers then is formed on this oxide liner.
Aforementioned and other characteristic of the present invention, aspect and advantage will more become apparent under the situation of following graphic and following detailed description of the present invention.
Description of drawings
Fig. 1 is a summary schematic diagram, in order to show the sectional drawing of the semiconductor device that goes out according to the construction of prior art method institute;
Fig. 2 is in order to show according to the semiconductor device of the embodiments of the invention manufacturing schematic diagram at first operation stage;
Fig. 3 is the schematic diagram of structure after the foundation embodiments of the invention form oxide liner in order to displayed map 2;
Fig. 4 is the schematic diagram of structure after the foundation embodiments of the invention are carried out source/drain extension implantation in order to displayed map 3;
Fig. 5 is the schematic diagram of structure after foundation embodiments of the invention dielectric layer in order to displayed map 4;
Fig. 6 be in order to the structure of displayed map 5 at this dielectric layer of foundation embodiments of the invention etching to form the schematic diagram of sidewall spacers after on this grid;
Fig. 7 carries out at the foundation embodiments of the invention in order to the structure of displayed map 6 to go deep into that source/drain is implanted and schematic diagram after forming this semiconductor device regions and source; And
Fig. 8 a to 8c is in order to show according to the disposable type alternate form of embodiments of the invention and the schematic diagram that utilizes this disposable type implant procedure at interval.
Embodiment
The present invention be in order to deal with solve in heat treatment process because of give birth to due to the outdiffusion of alloy is to the cover layer the source/drain of high electrical resistance and more tilt be connected problems such as reducing performance of transistors.With regard in a way, by being formed at the semiconductor device of the oxide liner that has thickness 100 dusts on base material and the grid, the present invention can solve aforesaid those problems.Etching is formed at nitride layer on this oxide liner to form nitride spacers, and this etching is made and ended on this oxide liner.By this thin oxide liner can prevent terminating in the follow-up heat treatment process previous implant the outdiffusion of alloy, it is unlikely to provide big alloy groove as known techniques.Therefore, more alloy can remain in this base material.Can cause the connection of giving birth to more low-resistance source/drain and more not tilting, use the lifting performance of transistors.
Fig. 2 is in order to the structure of semiconductor device in the first step that is shown in technology.In this schematic depiction, be to be formed on this base material 30 by the grid 32 that can for example form for materials such as polysilicons.The structure of this polysilicon gate 32 or for example be metal gate structure etc., can by as behind light lithography and etching step deposit spathic silicon lock electricity promptly formed in the first-class known techniques of silicon substrate.Also can form gate oxide (not graphic), use the generation gate dielectric in base material 30 and 32 of polysilicon gates.
As shown in Figure 3, after this grid 32 generates, deposition oxide liner 34.The typical method that forms this oxide liner is by haveing the knack of this operator electricity slurry known enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD) method for it.This oxide liner is the thickness that is deposited into less than 100 dusts, and this thickness can be between between 20 dust to 70 dusts in preferred embodiment.In better embodiment, this oxide liner thickness of silicon is less than 45 dusts.This oxide liner 34 is covered in the surface of this grid 32 and base material 30.
In Fig. 4, carry out source/drain according to known method and extend implantation is adjacent to this lock the 32nd with formation source/drain extension 36.This grid covers this base material 30 and directly implants the base material 30 under this grid 32 to prevent alloy.Although disclose the embodiment of a kind of order of process step of the present invention in the 3rd and 4 figure, so in other embodiment, the sequence of steps among the 3rd and 4 figure can be exchanged, and this extension implantation is to carry out prior to these oxide liner 34 depositions in view of the above.
In Fig. 5, for example the dielectric layer 38 for silicon nitride etc. is to be deposited on the oxide liner 34.This dielectric layer 38 can be by being deposited as conventional approaches such as chemical vapour deposition (CVD)s.Other material also can be used in this dielectric layer 38, and those materials have more optionally etching compared to oxide.
In Fig. 6, the nitrogenize in this dielectric layer 38 is that etched boundary has formed sidewall spacers 40.In this nitride etch process, this oxide liner 34 must be used the destruction that prevents this base material 30 as etch stop layer.Because this oxide liner 34 is compared thinner thickness with known techniques, therefore must be noted that the generation of over etching.In view of the above, can utilize high etch selectivity to form this sidewall spacers 40.This etch chemistries is necessary for high nitrogen oxygen ratio (nitride-to-oxide) selectivity, in order to do making this thin liner can be used as suitable etch stop layer.Illustrative chemical substance can comprise tetrafluoromethane (CF
4).Other comprises that in order to etched chemical substance or prescription electric paste etching or reactive ion etching etc. can comprise CF
4/ HBr/HeO
2And CL
2/ HBr/HeO
2
Fig. 7 is by carrying out the schematic diagram after deep implantation and follow-up heat treatment form regions and source 42 in order to the structure of displayed map 6.Go deep in the source/drain implantation process in this, this sidewall spacers 40 is used alloy as the usefulness of shielding and directly is implanted in the base material 30 under this sidewall spacers 40.Can utilize metering, implantation energy and the thermal annealing parameter commonly used.
In showing tremendous enthusiasm process, because the thickness of this oxide liner 34 can prevent that haply this liner from being become the alloy groove, so this thin-oxide liner 34 can prevent the outdiffusion that this regions and source 42 and source/drain extend alloy in 36.Therefore, more alloy is retained in the base material 30.This kind group effect can reduce this regions and source 42 and the resistance of source/drain extension 36 and being connected of more not tilting, and uses the lifting performance of transistors.
In another aspect, can be provided for depositing the high etching of program at interval and select film.In this program, utilize germanium oxide as disposable spacer material.This germanium oxide has the characteristic of Yu Shuizhong dissolving.This germanium oxide can be formed by sputtering way, or along with follow-up oxidation is formed by the germanium chemical vapour deposition (CVD).Then form at interval by the anisotropic dry-etching.Fig. 8 a is in order to be shown in germanium oxide 50 structures that are deposited on the liner of being made up of oxide, nitride or other material 52 at interval.
Disposable type can be used in the diverse ways at interval, and shown in Fig. 8 b, it is to form the back execution at interval in this to go deep into source/drain implantation 54 that a kind of illustration makes method.Because formed source/drain extension can't be born higher temperature after removing at interval, is high cycle of annealing so then can carry out than the known techniques temperature.Shown in Fig. 8 c, then deposit this interval 50 and carry out a small amount of doped-drain (Lightly Doped Drain; LDD) and process annealing.
The advantage of this germanium oxide be can be in water the removing of safety, and can be selected from known other thin-film material that is used for semiconductor technology.
The foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any personage who has the knack of this skill all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention, claim is listed as described later.
Claims (10)
1. semiconductor device comprises:
Base material (30);
Be formed at the grid (32) on this base material (30);
Be formed at the oxide liner (34) on this grid (32), this oxide liner (34) has the thickness less than 100 dusts; And
Be formed at this oxide liner (34) and go up nitride sidewall spacers (40).
2. device as claimed in claim 1 also is included in the source/drain elongated area that can keep in the heat treatment process being formed in this base material (30) and implants (36) and regions and source (42).
3. device as claimed in claim 2, wherein this oxide liner (34) thickness is less than 45 dusts.
4. method that forms semiconductor device comprises:
Go up formation grid (32) in base material (30);
And in the last oxide liner (34) that forms thickness less than 100 dusts of this base material (30) and grid (32);
Go up nitride layer (38) in this oxide liner (34); And
To form nitride spacers (40), this etch-stop is on this oxide liner (34) by this nitride layer of etching (38).
5. method as claimed in claim 4, wherein the step of this nitride layer of etching (38) comprises by having optionally this nitride layer of etch chemistries dry-etching (38) of very high nitrogen oxygen ratio.
One kind prevent alloy from the implantation region the overseas method that diffuses in the semiconductor device cover layer, comprising:
Implant the zone (36,42) of alloy to this base material (30); And
And in the last oxide liner (34) that forms thickness less than 100 dusts of this base material (30).
7. method as claimed in claim 6 also is included in and forms grid (32) before this alloy is implanted, and upward forms sidewall spacers (40) in grid (32) and oxide liner (34).
8. method as claimed in claim 7, wherein in the step that forms this sidewall spacers (40), be included in this grid (32) and go up nitride layer (38) with oxide liner (34), and by having optionally this nitride layer of dry-etching (38) of etching chemistry prescription anisotropic of high nitrogen oxygen ratio.
9. method as claimed in claim 8, wherein this etching chemistry prescription comprises CF
4/ HBr/HeO
2And CL
2/ HBr/HeO
2In at least a.
10. method as claimed in claim 8, wherein this etching chemistry prescription comprises chemical substance CF
4
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2103701A | 2001-12-19 | 2001-12-19 | |
| US10/021,037 | 2001-12-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1606801A true CN1606801A (en) | 2005-04-13 |
| CN1322565C CN1322565C (en) | 2007-06-20 |
Family
ID=21801954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028257502A Expired - Fee Related CN1322565C (en) | 2001-12-19 | 2002-12-19 | Semiconductor device comprising a thin oxide liner and method of manufacturing the same |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2005517285A (en) |
| KR (1) | KR20040068269A (en) |
| CN (1) | CN1322565C (en) |
| AU (1) | AU2002358269A1 (en) |
| DE (1) | DE10297582T5 (en) |
| GB (1) | GB2399222B (en) |
| WO (1) | WO2003054951A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820265A (en) * | 2011-03-16 | 2012-12-12 | 格罗方德半导体公司 | Performance enhancement in transistors by reducing the recessing of active regions and removing spacers |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583016B1 (en) * | 2002-03-26 | 2003-06-24 | Advanced Micro Devices, Inc. | Doped spacer liner for improved transistor performance |
| JP2008124441A (en) * | 2006-10-19 | 2008-05-29 | Tokyo Electron Ltd | Manufacturing method of semiconductor device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868617A (en) * | 1988-04-25 | 1989-09-19 | Elite Semiconductor & Sytems International, Inc. | Gate controllable lightly doped drain mosfet devices |
| US5714413A (en) * | 1995-12-11 | 1998-02-03 | Intel Corporation | Method of making a transistor having a deposited dual-layer spacer structure |
| US6472281B2 (en) * | 1998-02-03 | 2002-10-29 | Matsushita Electronics Corporation | Method for fabricating semiconductor device using a CVD insulator film |
| US6162692A (en) * | 1998-06-26 | 2000-12-19 | Advanced Micro Devices, Inc. | Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor |
| US6251764B1 (en) * | 1999-11-15 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to form an L-shaped silicon nitride sidewall spacer |
| US6294480B1 (en) * | 1999-11-19 | 2001-09-25 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an L-shaped spacer with a disposable organic top coating |
| US6156598A (en) * | 1999-12-13 | 2000-12-05 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a lightly doped source and drain structure using an L-shaped spacer |
| US6277700B1 (en) * | 2000-01-11 | 2001-08-21 | Chartered Semiconductor Manufacturing Ltd. | High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness |
-
2002
- 2002-12-19 JP JP2003555574A patent/JP2005517285A/en active Pending
- 2002-12-19 WO PCT/US2002/041103 patent/WO2003054951A1/en active Application Filing
- 2002-12-19 AU AU2002358269A patent/AU2002358269A1/en not_active Abandoned
- 2002-12-19 KR KR10-2004-7009490A patent/KR20040068269A/en not_active Application Discontinuation
- 2002-12-19 DE DE10297582T patent/DE10297582T5/en not_active Ceased
- 2002-12-19 GB GB0412884A patent/GB2399222B/en not_active Expired - Lifetime
- 2002-12-19 CN CNB028257502A patent/CN1322565C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820265A (en) * | 2011-03-16 | 2012-12-12 | 格罗方德半导体公司 | Performance enhancement in transistors by reducing the recessing of active regions and removing spacers |
| CN102820265B (en) * | 2011-03-16 | 2016-05-25 | 格罗方德半导体公司 | By reducing the depression of active region and removing interval body to promote performance of transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0412884D0 (en) | 2004-07-14 |
| WO2003054951A1 (en) | 2003-07-03 |
| KR20040068269A (en) | 2004-07-30 |
| JP2005517285A (en) | 2005-06-09 |
| GB2399222B (en) | 2005-07-20 |
| GB2399222A (en) | 2004-09-08 |
| CN1322565C (en) | 2007-06-20 |
| AU2002358269A1 (en) | 2003-07-09 |
| DE10297582T5 (en) | 2004-11-11 |
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