CN1320641C - Methods for forming structure and spacer and related FINFET - Google Patents
Methods for forming structure and spacer and related FINFET Download PDFInfo
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- CN1320641C CN1320641C CNB028300432A CN02830043A CN1320641C CN 1320641 C CN1320641 C CN 1320641C CN B028300432 A CNB028300432 A CN B028300432A CN 02830043 A CN02830043 A CN 02830043A CN 1320641 C CN1320641 C CN 1320641C
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 125000006850 spacer group Chemical group 0.000 title description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 97
- 230000003647 oxidation Effects 0.000 claims description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000011521 glass Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052792 caesium Inorganic materials 0.000 claims description 2
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 7
- 239000000126 substance Substances 0.000 abstract 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides some methods used for forming an isolation layer (44) used for first structures (24, 124), such as grid electrode structures of FinFET. Besides, an isolation layer is formed on at most part of a second structure (14), such as fins without harmfully changing the second structure. The first structure (24) having top parts (30, 130) hung above conductive lower parts (32, 132), and the isolation layer (44) below hanging substances (40, 140) are generated by the method. The hanging substances (40, 140) can be eliminated after the technology of the isolation layer. The part of the hanging substance protecting fins (14) for the FinFET is the region adjacent to and below the grid electrode structures (24, 124), and side wall of the fins (14) permit to be exposed to other technologies, such as selective silicon growth and injection. As a result, the methods provide the manufacture of fins (14) according to sizes, the formation of grid electrode structures (24, 124) and the isolation layer, and can not harmfully change (for example, the fins are eroded or an isolation layer is formed on the fins (14). The present invention likewise discloses a FinFET (100) comprising the grid electrode structures (24, 124) and the isolation layer (44).
Description
Technical field
The present invention relates generally to CMOS technology.
Background technology
Separator provides in complementary metal oxide semiconductors (CMOS) (CMOS) technology, with the universal architecture of the technogenic influence protecting a structure not to be subjected to adjacent structure is implemented.Must use the exemplary types of the cmos device of protectiveness separator therein is FinFET (FinFET) and MesaFET.For example, the FinFET grid that structurally also is included in except other parts on the part of each sidewall of thin, vertical silicon " fin " and extends along this part.In FinFET, need separator, be used to be blocked in the injection of gate edge and prevent that silicide is shorted to grid.There are many problems that relate to fin in conventional planar CMOS spacer processes.Especially, the common process that is formed for the separator of grid has caused the application of fin.If use conventional spacer processes, it is potential problems that the fin during the separator etching corrodes.When fin needed to approach singularly, any additional etching can stop the acquisition of required fin size.Another challenge is to form separator along grid rather than on fin sidewall and fin top, thereby the part fin that does not close on grid may be exposed to injection.In conventional spacer processes, because the three-dimensional character of FinFET also forms on the sidewall at fin at the separator that forms on the grid.In some cases, for example sidewall inject or the source drain extended peroid between, this sidewall spacers is undesirable.The separator of attempting to remove fin sidewall causes removing the separator on the grid that needs separator.Same problem is present in other cmos device that relates to MesaFET for example.
For above-mentioned reasons, in this area, need be used on the part at the most of first structure and second structure forming separator and during spacer processes, can not change improving one's methods of second structure nocuously.
Summary of the invention
The present invention relates to certain methods, be used to form the separator of the grid structure that is used for first structure such as FinFET, and on the part at the most in the fin district of second structure such as adjacent gate, form separator and can not change (for example, corrode or form separator) second structure nocuously thereon.This method produces has first structure (grid structure) of the top portion that overhangs on the lower part and the separator under the pendle.Can after spacer processes, remove pendle.Pendle is protected first structure, and if first structure and the second structure crossover, can protect part second structure.Example here is that by fin district contiguous among the FinFET of separator protection and under grid structure, wherein the sidewall of this fin is exposed to other technology as selective silicon growth and injection.What as a result, this method provided second structure can not change second structure by the formation of size manufacturing (sizing) and first structure and separator nocuously during spacer processes.The present invention relates to equally and comprising by the grid structure of this method formation and the FinFET of separator.
By more detailed description, of the present invention above-mentioned apparent with the further feature general to the specific embodiment of the present invention.
Description of drawings
With reference to following accompanying drawing, will describe embodiments of the invention in detail, wherein same label is represented same part, and wherein:
Fig. 1 shows the perspective view of the first pre-structure of the FinFET that comprises the fin that does not have grid material;
Fig. 2 A-B shows the cross-sectional view of first and second steps of this method;
Fig. 3 A-B shows the cross-sectional view of the third step of this method;
Fig. 4 A-B shows the cross-sectional view according to the 4th step of this method first embodiment;
Fig. 5 A-B shows the cross-sectional view according to the 4th step of this method second embodiment;
Fig. 6 A-B shows the cross-sectional view of the 5th step of this method;
Fig. 7 A-B shows the cross-sectional view of the 6th step of this method and the grid structure and relevant separator of gained.
Embodiment
Use description to now to form as first structure of grid structure and relevant separator and can not change the method for second structure nocuously.The present invention relates to description in the content that FinFET uses.For clear, grid structure is " first structure ", and fin is " second structure ".In the application of FinFET, be formed for the separator of grid, and because fin passes grid and form separator on the part of the fin of adjacent gate.Yet, should be appreciated that, this method of describing can be used for any device, wherein need to be formed for the separator of first structure and the separator of a part at the most that is formed for second structure (not having fully or a part), that is to say, if two structures are separated certain distance, this method can form separator fully not forming under the situation of separator on another structure on a structure.For example, two structures can be grids, and need separator in grid one, but do not need fully on another grid.Therefore, the term of first and second structures can be applied to during various CMOS forms.Yet,, will only describe the application of FinFET in detail in order to describe succinct purpose.It is to change by undesirable mode that phrase " changes " meaning nocuously.For example, in the application of FinFET, by forming separator or corrode fin on fin, the spacer processes on the grid may change fin nocuously.Relate to above in the example of grid, " changing nocuously " can be included on the grid that does not need separator and form separator.
With reference to the accompanying drawings, Fig. 1 is the gate etch perspective view of the first pre-structure 10 of FinFET afterwards.In this moment of technology, structure 10 comprises the substrate 12 that is formed with monocrystalline silicon fin 14 thereon.The grid structure (not shown) forms on fin 14 the most at last.Also provide hard mask 16, with protection fin 14 during technology.For example, hard mask 16 can be that dioxy (oxygen) is changed silicon or silicon nitride.The actual process that is used to form this first pre-structure 10 can comprise the hard mask 16 of deposit, and hard mask 16 of etching and following silicon to be to produce fin 14, carries out the sacrificial oxidation of silicon and gate oxidation to produce structure oxide 18.Should be appreciated that above-mentioned technology only is exemplary, structure shown in other technology also can realize.As shown in the figure, fin 14 is ready to produce grid structure and the separator that is used for grid structure.
Fig. 2-7 shows and is used for during spacer processes, is formed for the separator and the method for the separator of a part at the most that is used for fin of grid.In the drawings, the cross-sectional view that illustrates the A-A that passes fin 14 as shown in Figure 1 of mark ' A ', and the cross-sectional view that illustrates the B-B that passes fin 14 as shown in Figure 1 (by the grid structure of former formation) of mark ' B '.
In the first step shown in Fig. 2 A-B, deposit is used to produce first material 20 of grid structure on fin 14.Fig. 2 A-B also shows second step, wherein forms second material 22,122 on first material 20.(second material 22,122 comprises double design, because this material can be by two kinds of multi-form providing, as will be described in more detail below.) equally as will be described in more detail below, second material 22,122 is different with first material 20.
Fig. 3 A-B shows next step, wherein forms grid structure 24 in first material 20 and second material 22,122.Formation can be included in apply on first material and second material 22,122 and composition (for example, use imprint lithography) as the hard mask 26 of oxide (TEOS), and etching material is with formation grid structure 24.Shown in Fig. 3 B, equally these steps are applied to the final source electrode and the drain region 28 of fin 14.Then, remove hard mask 26 by known mode.
Fig. 4 A-B and 5A-B show two embodiment of next step, wherein form second material 22,122, to overhang on first material 20.As mentioned above, second material 22,122 is different with first material 20.
Fig. 4 A-B shows first embodiment, wherein uses polysilicon (hereinafter for ' polysilicon ') to form second material 22 (in the step shown in Fig. 2 A-B), thereby second material 22 has than first material 20 oxidation rate faster.For these different oxidations rate are provided in one embodiment, second material 22 can be the part by first material of known manner implanted dopant.Impurity can be that any polysilicon second material 22 that makes is with the material than the oxidation of non-impurity-doped polysilicon faster rate.For example, impurity can be arsenic (As) (preferably), germanium (Ge), caesium (Cs), argon (Ar) or fluorine (F) or its combination.In another embodiment, can be on first material deposit have than first material 20, second material 22 of oxidation rate faster, for example, use polycrystalline germanium-alloyed silicon.First material 20 can be, for example, and the non-impurity-doped polysilicon.According to present embodiment,, form second material 22 to overhang on first material 20 by as under 800-950 ℃, carrying out oxidation.With respect to the fin 14 and first material, oxidations rate different between the material have produced thicker oxide in second material 22 of grid structure 24.As a result, produced the pendle 40 of the fin 14 that closes on first material 20.Fig. 4 A-B shows resulting structures, and wherein second material 22 forms the top portion 30 that the conductive lower portion that overhangs grid structure 24 is divided the grid structure 24 on 32.Oxidation technology also can make thin oxide layer 34 (for example, than second material 22 thin about 10 times) form on the side of the side (that is, the lower part 32) of first material 20 of grid structure 24 outsides and fin 14.Oxide skin(coating) 34 allows to keep the width of fin 14 and does not oxidize away fin.
Fig. 5 A-B shows second, optional embodiment, is used to form second material 122 that overhangs on first material 20.In this case, provide second material 122 (in the step shown in Fig. 2 A-B) with any material with hot reflux characteristic different with first material 20.In one embodiment, provide first material 20 with polysilicon or as the metal of cobalt silicide or tungsten, and provide second material 122 with glass as boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).So, form the step overhang second material 122 on first material 20 and comprise and carry out thermal process, so that material 122 refluxes and forms pendle 140.Thermal process can comprise, for example, in the non-oxidation environment, heats at least the second material about 10 minutes down at about 850 ℃.Fig. 5 A-B shows resulting structures, and wherein second material 122 forms the top portion 130 that the conductive lower portion that overhangs grid structure 124 is divided the grid structure 124 on 132.
Be also noted that Fig. 4 A-B and Fig. 5 A-B, should be appreciated that, shown in the shape of second material 22,122 can change according to embodiment that uses and the concrete technology that provides.Therefore, though accompanying drawing has exemplified the bulbous that is used for material 20,22 and 122 or the shape of umbrella, also can provide the pendle of other shape.
Next step is included in pendle and forms separator 40,140 times.Can on the structure of above-mentioned arbitrary embodiment, form separator.Yet, cause for simplicity, Fig. 6 A-B and Fig. 7 A-B only show the embodiment of Fig. 4 A-B.In an embodiment who is used to form separator, conformal deposited insolated layer materials 42 is shown in Fig. 6 A-B.Insolated layer materials can be, for example, and silicon nitride, silica or its combination.At last, shown in Fig. 7 A-B, use orientation reaction ion etching etch isolates material 42, this technology is removed except all the local materials below the pendle 40,140, to form separator 44.
Then can finish the technology (not shown).This technology can comprise, for example, removes oxide 34 (if used doped polycrystalline silicon, oxide will keep as top portion 30) from the side of fin 14 or removes top portion 130 from grid structure 124 (if use), that is, and glass.In the application of FinFET, final technology can comprise, for example, injection is with set threshold voltage (Vt), the source/drain regions 28 of doping fin 14, selective silicon is grown to widen the source/drain regions 28 on the fin 14, removes residual oxide and forms cobalt silicide (CoSi), conventional contact process utilizes the proper metal level to finish etc.
Gained FinFET 100 shown in Fig. 7 A-B also comprises except other parts: comprise that conductive lower portion divides 32,132 and the grid structure 24,124 of the top portion 30,130 of dangling, extend through the fin 14 of lower part, and be positioned at contiguous conductive lower portion and divide separator 44 under the top portion 30,130 of 32,132 grid structure 21,124.Top portion 30,130 is made up of the material (for example, oxide or glass) different with the material (for example, polysilicon) of above-mentioned lower part 32,132.
In the superincumbent description, " grid structure " 24,124 is described to comprise top portion 30,130 and lower part 32,132.Yet, should be appreciated that top portion 30,130 can finally not form the effective or active part of the actual gate of use.For example, can remove at least a portion of top portion 30,130 and/or pendle 40,140, allow to form and the contacting of the lower part 32,132 of grid structure 24,124.
Though described the present invention in conjunction with some preferred embodiments, those skilled in the art should be appreciated that, can implement the present invention in the spirit and scope of appended claims in every way.
Industrial usability
The present invention is for the separation layer of the grid that is formed for FinFET and in the at the most part of fin Upper formation separation layer and can detrimentally not change fin be useful.
Claims (21)
1. one kind is used to form separator (44) that is used for first structure (24,124) and the method that forms separator on the part at the most of second structure (14), and this method may further comprise the steps:
Deposit first material (20);
On described first material, form second material (22,122);
Utilize described first and second materials to form described first structure;
Described second material is overhang on described first material to form pendle (40,140); And
Under described pendle, form separator (44).
2. according to the process of claim 1 wherein that described second structure (14) is formed by monocrystalline silicon, and described first material (20) is formed by polysilicon.
3. form described second material (22) so that described second material has than described first material oxidation rate faster according to the process of claim 1 wherein.
4. according to the method for claim 3, wherein said second material comprises a kind of impurity, described impurity comprise be selected from following at least a: arsenic, germanium, caesium, argon and fluorine.
5. according to the method for claim 3, wherein said second material is the polycrystalline germanium-alloyed silicon of deposit.
6. according to the method for claim 3, wherein make the described step that described second material dangles comprise oxidation, with owing to form described pendle with respect to the different oxidations rate of described second material of described first material (20) (22).
7. according to the method for claim 3, described step that described second material dangles is included on the side of described first structure (24) and described second structure (14) forms oxide (34).
8. according to the process of claim 1 wherein that described second material (122) has the hot reflux characteristic different with described first material.
9. method according to Claim 8, wherein said second material (122) are a kind of in boron-phosphorosilicate glass and the phosphorosilicate glass.
10. method according to Claim 8 wherein makes the described step that described second material dangles comprise described second material of heating, so that described second material reflow is to form described pendle (40,140).
11. according to the process of claim 1 wherein that the described step that forms described separator (44) comprises:
Deposit insolated layer materials (42); And
Directional etch is removed except the described insolated layer materials under the described pendle (40,140).
12. according to the method for claim 11, wherein said insolated layer materials (42) is at least a in silicon nitride and the silica.
13. according to the process of claim 1 wherein that described first structure (24,124) is a grid, and described second structure (14) is the fin of FinFET (100).
14. one kind is used to form the grid structure (24,124) that is used for FinFET and the method for separator (44), this method may further comprise the steps:
Fin (14) at described FinFET is gone up deposit first material (20);
Form second material (22,122) on described first material, wherein said second material has than described first material oxidation rate faster;
Utilize described first material and described second material to form described grid structure;
Oxidation so that described second material overhang on described first material to form pendle (40); And
Under described pendle, form separator (44).
15. according to the method for claim 14, wherein said fin (14) is formed by monocrystalline silicon, and described first material (20) is a polysilicon.
16. according to the method for claim 14, wherein form polysilicon described second material (22) so that described second material have than described first material oxidation rate faster.
17. according to the method for claim 14, wherein said oxidation step also forms oxide (34) on the side of described fin (14) and grid structure (24).
18. according to the method for claim 14, the described step that wherein forms described separator (44) comprises:
Deposit insolated layer materials (42); And
Etching is removed except the described insolated layer materials under the described pendle (40).
19. a FinFET comprises:
Grid structure (24,124) comprises conductive lower portion branch (32,132) and the top portion of dangling (30,130);
Fin (14) extends through described lower part; And
Separator (44) is positioned under the top portion of the described grid structure that is close to described lower part.
20. according to the FinFET of claim 19, wherein said top portion (30,130) is by a kind of formation the in oxide and the glass, and described lower part (32,132) are formed by polysilicon.
21. according to the FinFET of claim 19, wherein said separator (44) is around the part of the described fin (14) of described lower part (32,132) and contiguous described grid structure (24,124).
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2002/040869 WO2004059727A1 (en) | 2002-12-19 | 2002-12-19 | Methods of forming structure and spacer and related finfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1714441A CN1714441A (en) | 2005-12-28 |
| CN1320641C true CN1320641C (en) | 2007-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028300432A Expired - Fee Related CN1320641C (en) | 2002-12-19 | 2002-12-19 | Methods for forming structure and spacer and related FINFET |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1573804A4 (en) |
| JP (1) | JP4410685B2 (en) |
| CN (1) | CN1320641C (en) |
| AU (1) | AU2002364088A1 (en) |
| WO (1) | WO2004059727A1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6951783B2 (en) * | 2003-10-28 | 2005-10-04 | Freescale Semiconductor, Inc. | Confined spacers for double gate transistor semiconductor fabrication process |
| US7473593B2 (en) | 2006-01-11 | 2009-01-06 | International Business Machines Corporation | Semiconductor transistors with expanded top portions of gates |
| US7341902B2 (en) * | 2006-04-21 | 2008-03-11 | International Business Machines Corporation | Finfet/trigate stress-memorization method |
| KR100838378B1 (en) * | 2006-09-29 | 2008-06-13 | 주식회사 하이닉스반도체 | Method for fabricating fin transistor |
| KR100801315B1 (en) | 2006-09-29 | 2008-02-05 | 주식회사 하이닉스반도체 | Method of fabricating semiconductor device with the finfet transistor |
| US8889495B2 (en) * | 2012-10-04 | 2014-11-18 | International Business Machines Corporation | Semiconductor alloy fin field effect transistor |
| KR102030329B1 (en) * | 2013-05-30 | 2019-11-08 | 삼성전자 주식회사 | Semiconductor device and method for fabricating the same |
| US9773869B2 (en) * | 2014-03-12 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| KR102504165B1 (en) | 2014-09-26 | 2023-02-28 | 인텔 코포레이션 | Selective gate spacers for semiconductor devices |
| US9564370B1 (en) | 2015-10-20 | 2017-02-07 | International Business Machines Corporation | Effective device formation for advanced technology nodes with aggressive fin-pitch scaling |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475890B1 (en) * | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
| US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
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| JP3393286B2 (en) * | 1995-09-08 | 2003-04-07 | ソニー株式会社 | Pattern formation method |
| US5567639A (en) * | 1996-01-04 | 1996-10-22 | Utron Technology Inc. | Method of forming a stack capacitor of fin structure for DRAM cell |
| DE19717363C2 (en) * | 1997-04-24 | 2001-09-06 | Siemens Ag | Manufacturing process for a platinum metal structure using a lift-off process and use of the manufacturing process |
| JP3519589B2 (en) * | 1997-12-24 | 2004-04-19 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor integrated circuit |
| US5994192A (en) * | 1998-05-29 | 1999-11-30 | Vanguard International Semiconductor Corporation | Compensation of the channel region critical dimension, after polycide gate, lightly doped source and drain oxidation procedure |
| DE10012112C2 (en) * | 2000-03-13 | 2002-01-10 | Infineon Technologies Ag | Bridge field effect transistor and method for producing a bridge field effect transistor |
| US6562665B1 (en) * | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
| US6492212B1 (en) * | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
-
2002
- 2002-12-19 JP JP2004563141A patent/JP4410685B2/en not_active Expired - Fee Related
- 2002-12-19 WO PCT/US2002/040869 patent/WO2004059727A1/en active Search and Examination
- 2002-12-19 EP EP02798557A patent/EP1573804A4/en not_active Withdrawn
- 2002-12-19 AU AU2002364088A patent/AU2002364088A1/en not_active Abandoned
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6475890B1 (en) * | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
| US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4410685B2 (en) | 2010-02-03 |
| EP1573804A4 (en) | 2006-03-08 |
| CN1714441A (en) | 2005-12-28 |
| EP1573804A1 (en) | 2005-09-14 |
| WO2004059727A1 (en) | 2004-07-15 |
| JP2006511092A (en) | 2006-03-30 |
| AU2002364088A1 (en) | 2004-07-22 |
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